Computer Architecture MCQ Multiple Choice Questions

Q: 1. The address in the main memory is known as

Correct Answer is: None of the above

Q: 2. The addressing mode which makes use of in-direction pointers is

Correct Answer is: offset addressing mode

Q: 5. The algorithm which removes the recently used page first is

Correct Answer is: None of the mentioned

Q: 7. The benefit of using this approach is

Correct Answer is: It increases the speed of operation

Q: 8. The bits 1 & 1 are recorded as............in bit-pair recording.

Correct Answer is: both -1 and 0

Q: 14. The condition flag Z is set to 1 to indicate

Correct Answer is: There is no empty register available

Q: 15. The contention for the usage of a hardware device is called

Correct Answer is: None of the mentioned

Q: 16. The disadvantage of the EPROM chip is

Correct Answer is: The need to remove the chip physically to reprogram it

Q: 17. The drawback of building a large memory with DRAM is

Correct Answer is: All of the mentioned

Q: 18. The effective address of the following instruction is MUL 5(R1,R2).

Correct Answer is: 5*([R1]+[R2])

Computer Architecture Multiple Choice Questions (MCQs) are essential practice tools for students and exam aspirants. These questions help reinforce key concepts and prepare you for various assessments and interviews.

About Computer Architecture MCQ Questions

Computer Architecture MCQs cover a wide range of topics, including processor design, memory hierarchy, instruction sets, and data paths. These questions are designed to test your understanding of how computer systems are structured and how they function at a hardware level.

Why Practice Computer Architecture Objective Questions?

Practicing Computer Architecture MCQs offers several benefits. It helps reinforce your knowledge, prepares you for exams and interviews, and ensures you have a solid grasp of the fundamental concepts. Regular practice can improve your problem-solving skills and boost your confidence.

Who Should Use These MCQs?

Computer Architecture MCQ Questions for Practice

1. The address in the main memory is known as

Logical address
Physical address
Memory address
None of the above

2. The addressing mode which makes use of in-direction pointers is

Indirect addressing mode
Index addressing mode
Relative addressing mode
offset addressing mode

3. The addressing mode, where you directly specify the operand value is

Immediate
Direct
Definite
Relative

4. The addressing mode/s, which uses the PC instead of a general purpose register is

Indexed with offset
Relative
Direct
Both Indexed with offset and direct

5. The algorithm which removes the recently used page first is

LRU
MRU
OFM
None of the mentioned

6. The algorithm which replaces the block which has not been referenced for a while is called

LRU
ORF
Direct
Both LRU and ORF

7. The benefit of using this approach is

It is cost effective
It is highly efficient
It is very reliable
It increases the speed of operation

8. The bits 1 & 1 are recorded as............in bit-pair recording.

-1
1
both -1 and 0

9. The bus used to connect the monitor to the CPU is

PCI bus
SCSI bus
Memory bus
Rambus

10. The chip can be disabled or cut off from an external connection using

Chip select
LOCK
ACPT
RESET

11. The collection of 8-bits is called as

Byte
Nibble
Word
Record

12. The collection of the above mentioned entities where data is stored is called

Block
Set
Word
Byte

13. The computer architecture aimed at reducing the time of execution of instructions is

CISC
RISC
ISA
ANNA

14. The condition flag Z is set to 1 to indicate

The operation has resulted in an error
The operation requires an interrupt call
The result is zero
There is no empty register available

15. The contention for the usage of a hardware device is called

Structural hazard
Stalk
Deadlock
None of the mentioned

16. The disadvantage of the EPROM chip is

The high cost factor
The low efficiency
The low speed of operation
The need to remove the chip physically to reprogram it

17. The drawback of building a large memory with DRAM is

The large cost factor
The inefficient memory organization
The Slow speed of operation
All of the mentioned

18. The effective address of the following instruction is MUL 5(R1,R2).

5+R1+R2
5+(R1*R2)
5+[R1]+[R2]
5*([R1]+[R2])

19. The fastest data access is provided using

Caches
DRAMs
SRAMs
Registers

20. The fetch and execution cycles are interleaved with the help of

Modification in processor architecture
Clock
Special unit
Control unit

21. The main advantage of multiple bus organization over a single bus is

Reduction in the number of cycles for execution
Increase in size of the registers
Better Connectivity
None of the mentioned

22. The main memory in a personal computer is made of

Static RAM
Both c and d
Cache memory
Dynamic RAM

23. The main virtue for using single Bus structure is

Fast data transfers
Cost effective connectivity and speed
Cost effective connectivity and ease of attaching peripheral devices
None of the mention

24. The memory blocks are mapped on to the cache with the help of

Hash functions
Vectors
Mapping functions
None of the mentioned

25. The method of accessing the I/O devices by repeatedly checking the status flags is

Program-controlled I/
Memory-mapped I/O
I/O mapped
None of the mentioned

26. The method of mapping the consecutive memory blocks to consecutive cache blocks is called

Set associative
Associative
Direct
Indirect

27. The method of synchronizing the processor with the I/O device in which the device sends a signal when it is ready is?

Exceptions
Signal handling
Interrupts
DMA

28. The method which offers higher speeds of I/O transfers is

Interrupts
Memory mapping
Program-controlled I/O
DMA

29. The minimum time delay between two successive memory read operations is

Cycle time
Latency
Delay
None of the mentioned

30. The multiplicand and the control signals are passed through to the n-bit adder via

MUX
DEMUX
Encoder
Decoder

Computer Architecture MCQ Multiple Choice Questions for Practice

About Computer Architecture MCQ Questions

Why Practice Computer Architecture Objective Questions?

Who Should Use These MCQs?

Computer Architecture MCQ Questions for Practice

1. The address in the main memory is known as

2. The addressing mode which makes use of in-direction pointers is

3. The addressing mode, where you directly specify the operand value is

4. The addressing mode/s, which uses the PC instead of a general purpose register is

5. The algorithm which removes the recently used page first is

6. The algorithm which replaces the block which has not been referenced for a while is called

7. The benefit of using this approach is

8. The bits 1 & 1 are recorded as............in bit-pair recording.

9. The bus used to connect the monitor to the CPU is

10. The chip can be disabled or cut off from an external connection using

11. The collection of 8-bits is called as

12. The collection of the above mentioned entities where data is stored is called

13. The computer architecture aimed at reducing the time of execution of instructions is

14. The condition flag Z is set to 1 to indicate

15. The contention for the usage of a hardware device is called

16. The disadvantage of the EPROM chip is

17. The drawback of building a large memory with DRAM is

18. The effective address of the following instruction is MUL 5(R1,R2).

19. The fastest data access is provided using

20. The fetch and execution cycles are interleaved with the help of

21. The main advantage of multiple bus organization over a single bus is

22. The main memory in a personal computer is made of

23. The main virtue for using single Bus structure is

24. The memory blocks are mapped on to the cache with the help of

25. The method of accessing the I/O devices by repeatedly checking the status flags is

26. The method of mapping the consecutive memory blocks to consecutive cache blocks is called

27. The method of synchronizing the processor with the I/O device in which the device sends a signal when it is ready is?

28. The method which offers higher speeds of I/O transfers is

29. The minimum time delay between two successive memory read operations is

30. The multiplicand and the control signals are passed through to the n-bit adder via

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Computer Architecture MCQ Multiple Choice Questions for Practice

About Computer Architecture MCQ Questions

Why Practice Computer Architecture Objective Questions?

Who Should Use These MCQs?

Computer Architecture MCQ Questions for Practice

1. The address in the main memory is known as

2. The addressing mode which makes use of in-direction pointers is

3. The addressing mode, where you directly specify the operand value is

4. The addressing mode/s, which uses the PC instead of a general purpose register is

5. The algorithm which removes the recently used page first is

6. The algorithm which replaces the block which has not been referenced for a while is called

7. The benefit of using this approach is

8. The bits 1 & 1 are recorded as............in bit-pair recording.

9. The bus used to connect the monitor to the CPU is

10. The chip can be disabled or cut off from an external connection using

11. The collection of 8-bits is called as

12. The collection of the above mentioned entities where data is stored is called

13. The computer architecture aimed at reducing the time of execution of instructions is

14. The condition flag Z is set to 1 to indicate

15. The contention for the usage of a hardware device is called

16. The disadvantage of the EPROM chip is

17. The drawback of building a large memory with DRAM is

18. The effective address of the following instruction is MUL 5(R1,R2).

19. The fastest data access is provided using

20. The fetch and execution cycles are interleaved with the help of

21. The main advantage of multiple bus organization over a single bus is

22. The main memory in a personal computer is made of

23. The main virtue for using single Bus structure is

24. The memory blocks are mapped on to the cache with the help of

25. The method of accessing the I/O devices by repeatedly checking the status flags is

26. The method of mapping the consecutive memory blocks to consecutive cache blocks is called

27. The method of synchronizing the processor with the I/O device in which the device sends a signal when it is ready is?

28. The method which offers higher speeds of I/O transfers is

29. The minimum time delay between two successive memory read operations is

30. The multiplicand and the control signals are passed through to the n-bit adder via

Your Score

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