Correct Answer is: Computer Service Architecture

Correct Answer is: Risk Instruction Source Compiler

Correct Answer is: Register Transfer Notation

The memory and I/O devices have an associated address space

The I/O devices and the memory share the same address space

The I/O devices have a separate address space

A part of the memory is specifically set aside for the I/O operation

Risk Instruction Source Compiler

Reduce Instruction Set Computer

Risk Instruction Sequential Compilation

Computer Architecture MCQ Multiple Choice Questions Answers for Practice

Q: 1. ...........are used to overcome the difference in data transfer speeds of various devices.

Correct Answer is: Multiple Buses

Q: 2. A sequence of control words corresponding to a control sequence is called

Correct Answer is: None of the mentioned

Q: 3. Both the CISC and RISC architectures have been developed to reduce the

Correct Answer is: Semantic gap

Q: 4. Computer address bus is

Correct Answer is: Multidirectional

Q: 6. During a write operation if the required block is not present in the cache then............occurs.

Correct Answer is: Write latency

Q: 12. In memory-mapped I/O

Correct Answer is: The memory and I/O devices have an associated address space

Q: 13. In micro-programmed approach, the signals are generated by

Correct Answer is: Machine instructions

Q: 14. In multiple Bus organization, the registers are collectively placed and referred as

Correct Answer is: Register file

Q: 15. In the case of, Zero-address instruction method the operands are stored in

Correct Answer is: Accumulators

1. ...........are used to overcome the difference in data transfer speeds of various devices.

Speed enhancing circuitory
Bridge circuits
Multiple Buses
Buffer registers

2. A sequence of control words corresponding to a control sequence is called

Micro routine
Micro function
Micro procedure
None of the mentioned

3. Both the CISC and RISC architectures have been developed to reduce the

Cost
Time delay
Semantic gap
All of the mentioned

4. Computer address bus is

Multidirectional
Bidirectional
Unidirectional
None of the above

5. CSA stands for?

Computer Speed Addition
Carry Save Addition
Computer Service Architecture
None of the mentioned

6. During a write operation if the required block is not present in the cache then............occurs.

Write latency
Write hi
Write delay
Write miss

7. Every time a new instruction is loaded into IR the output of..........is loaded into UPC.

Starting address generator
Loader
Linker
Clock

8. If the decimal point is placed to the right of the first significant digit, then the number is called

Orthogonal
Normalized
Determinate
None of the mentioned

9. In double precision format, the size of the mantissa is

32 bit
52 bit
64 bit
72 bit

10. In IEEE 32-bit representations, the mantissa of the fraction is said to occupy............bits.

11. In LRU, the referenced blocks counter is set to’0′ and that of the previous blocks are incremented by one and others remain same, in the case of

Hit
Miss
Delay
None of the mentioned

12. In memory-mapped I/O

The I/O devices and the memory share the same address space
The I/O devices have a separate address space
The memory and I/O devices have an associated address space
A part of the memory is specifically set aside for the I/O operation

13. In micro-programmed approach, the signals are generated by

Machine instructions
System programs
Utility tools
None of the mentioned

14. In multiple Bus organization, the registers are collectively placed and referred as

Set registers
Register file
Register Block
Map registers

15. In the case of, Zero-address instruction method the operands are stored in

Registers
Accumulators
Push down stack
Cache

16. In which of the following term the performance of cache memory is measured?

Chat ratio
Hit ratio
Copy ratio
Data ratio

17. In..............protocol the information is directly written into the main memory.

Write through
Write back
Write first
None of the mentioned

18. Individual control words of the micro routine are called as

Micro task
Micro operation
Micro instruction
Micro command

19. RISC stands for

Reduce Instruction Set Computer
Risk Instruction Sequential Compilation
Risk Instruction Source Compiler
None of the above

20. RTN stands for

Register Transfer Notation
Register Transmission Notation
Regular Transmission Notation
Regular Transfer Notation

21. Subtraction in computers is carried out by

1's complement
2's complement
3's complement
9's complement

22. The address in the main memory is known as

Logical address
Physical address
Memory address
None of the above

23. The addressing mode which makes use of in-direction pointers is

Indirect addressing mode
Index addressing mode
Relative addressing mode
offset addressing mode

24. The addressing mode, where you directly specify the operand value is

Immediate
Direct
Definite
Relative

25. The addressing mode/s, which uses the PC instead of a general purpose register is

Indexed with offset
Relative
Direct
Both Indexed with offset and direct

26. The algorithm which removes the recently used page first is

LRU
MRU
OFM
None of the mentioned

27. The algorithm which replaces the block which has not been referenced for a while is called

LRU
ORF
Direct
Both LRU and ORF

28. The benefit of using this approach is

It is cost effective
It is highly efficient
It is very reliable
It increases the speed of operation

29. The bits 1 & 1 are recorded as............in bit-pair recording.

-1
1
both -1 and 0

30. The bus used to connect the monitor to the CPU is

PCI bus
SCSI bus
Memory bus
Rambus

Computer Architecture Multiple Choice Questions (MCQs) are essential practice tools for students and exam aspirants. These questions help reinforce key concepts and prepare you for various assessments and interviews.

About Computer Architecture MCQ Questions

Computer Architecture MCQs cover a wide range of topics, including processor design, memory hierarchy, instruction sets, and data paths. These questions are designed to test your understanding of how computer systems are structured and how they function at a hardware level.

Why Practice Computer Architecture Objective Questions?

Practicing Computer Architecture MCQs offers several benefits. It helps reinforce your knowledge, prepares you for exams and interviews, and ensures you have a solid grasp of the fundamental concepts. Regular practice can improve your problem-solving skills and boost your confidence.

Who Should Use These MCQs?

Students preparing for school or college exams
Competitive exam aspirants
Candidates preparing for interviews