VLSI Design MCQs Quiz Multiple Choice Questions & Answers

1. What advantage does the 74LSXX series device have over standard TTL?

1. low power consumption
2. low power consumption and reduced propagation delay
3. higher propagation delay
4. reduced propagation delay

2. What advantage does the 74LXX series device have over standard TTL?

1. higher propagation delay
2. low power consumption
3. lower voltage requirements
4. reduced propagation delay

3. What advantage does the 74SXX series device have over standard TTL?

1. low power consumption
2. reduced propagation delay
3. higher propagation delay
4. lower voltage requirements

4. When a CMOS gate output connects to a TTL gate, which circuit is needed?

1. a pull-down resistor
2. a CMOS buffer
3. a decoupling capacitor
4. a pull-up resistor

5. When a TTL gate output connects to a CMOS gate, what must be added to the circuit?

1. a pull-down resistor
2. an open-collector gate
3. a decoupling capacitor
4. a pull-up resistor

6. When interfacing CMOS to TTL what potential problem must be overcome?

1. The output current may be too great.
2. The high voltage may be too low.
3. There may be insufficient current.
4. The low output voltage may be insufficient.

7. When the outputs of several open-collector TTL gates are connected together, the gate outputs

1. are ANDed together.
2. produce more voltage.
3. produce more fan-out.
4. usually burn out.

8. When the outputs of several standard TTL gates are connected together, the gate outputs

1. usually burn out.
2. produce more voltage.
3. enable new logic configurations.
4. produce more fan-out.

9. Which alteration is made in the manufacture of a TTL gate to create an open-collector output?

1. The output transistors are missing.
2. The top output transistor is missing.
3. The output transistors are replaced by diodes.
4. The input transistor is replaced by a diode.

10. Which of the following are not characteristics of TTL logic gates?

1. CMOS transistors
2. Multiemitter transistors
3. Totem-pole output
4. Bipolar transistors

11. Which of the following input levels would not be a valid HIGH for a TTL gate?

1. 1.8 V
2. All are valid.
3. 2.4 V
4. 2.1 V

12. Which of the following is a concern when using CMOS type devices?

1. fan out
2. under voltage
3. mechanical shock
4. electrostatic discharge

13. Which of the following is a special type of transistor used in the TTL series to improve speed characteristics?

1. Brattain
2. Schottky
3. Belrus
4. Shockley

14. When setting the voltage for an external device that must interface with an FPGA, you must change the value of

1. VDDiO
2. VCCIN
3. VCCIO
4. VDDIN

15. Which of the following digital IC logic families is most susceptible to static discharge?

1. MOS
2. TTL
3. RTL
4. ECL

16. Which of the following is not a common logic family used today?

1. TTL
2. CMOS
3. RTL
4. ECL

17. Which of the following is not a solution to interface problems between CMOS and TTL?

1. level-shifter
2. buffer
3. pull-up resistor
4. pull-down resistor

18. Which of the following levels would not be a valid LOW for a TTL gate?

1. 1.0 V
2. All are valid.
3. 0.1 V
4. 0.7 V

19. Which of the following output levels would be a valid HIGH for a TTL gate?

1. 5.1 V
2. All are valid.
3. 3.0 V
4. 2.6 V

20. Which of the following output levels would not be a valid LOW for a TTL gate?

1. 0.2 V
2. All are valid.
3. 0.3 V
4. 0.5 V

21. Which potential problem must be overcome when interfacing TTL to CMOS?

1. The HIGH output voltage may be too high.
2. The output current may not be sufficient.
3. The HIGH output voltage may be too low.
4. The LOW output voltage may be too high.

22. Which specialized device distinguishes the 74LSXX circuits from standard 74XX circuits?

1. a multiemitter transistor
2. totem-pole output transistor
3. a Schottky diode
4. a CMOS transistor

23. A common means for comparing the propagation delays and the power dissipation of various logic gates is the

1. speed-power product.
2. noise margin.
3. fan-out.
4. power requirements.

24. A family of logic devices designed for extremely high speed applications is called

1. PMOS
2. TTL
3. NMOS
4. ECL

25. An invalid input voltage for a TTL logic gate would be

1. greater than 2.0 V.
2. between 0.8 V and 2.0 V.
3. less than 0.8 V.
4. greater than 2.0 V but less than 5.0 V.

26. An open-collector TTL gate

1. must have an external ground connected to the output to produce a LOW.
2. must have a transistor added to the output to produce a HIGH.
3. must have an external pull-up resistor to produce a LOW.
4. must have an external pull-up resistor to produce a HIGH.

27. An open-collector TTL gate

1. cannot source or sink current.
2. can sink more current than a standard TTL gate.
3. can sink current but cannot source current.
4. can source current but cannot sink current.

28. Each input on a TTL gate is connected to the transistors

1. gate.
2. emitter.
3. base.
4. collector.

29. Fan-out for a typical TTL gate is

1. 54
2. 100
3. 10
4. 4

30. In order to interface an FPGA with an external device, you must set the value of the

1. source current.
2. all of the above
3. sink current.
4. external power supply.

31. One advantage that MOSFET transistors have over bipolar transistors is

1. high input impedance.
2. low input impedance.
3. reduced propagation delay.
4. higher switching speed.

32. The 54XX TTL IC series is the military version and has

1. higher current output capability.
2. all of the above.
3. a wider temperature range.
4. more stringent power supply requirements.

33. The abbreviated designation for input current with a HIGH input is

1. IIL.
2. IOL.
3. VIH.
4. IIH.

34. The abbreviated designation for input current with a LOW input is

1. IIL.
2. IOL.
3. VIH.
4. IIH.

35. The abbreviated designation for output current with a HIGH output is

1. IIH.
2. IOL.
3. IOH.
4. IIL.

36. The abbreviated designation for output current with a LOW output is

1. IOH.
2. IIH.
3. OOL.
4. IOL.

37. The abbreviated designator for a HIGH input voltage is

1. VIL.
2. VOL.
3. VOH.
4. VIH.

38. The abbreviated designator for a HIGH output voltage is

1. VIH.
2. VOL.
3. VIL.
4. VOH.

39. The abbreviated designator for a LOW input voltage is

1. VOL.
2. VIH.
3. VIL.
4. VOH.

40. The abbreviated designator for a LOW output voltage is

1. VOL.
2. VIH.
3. VOH.
4. VIL.

41. The abbreviation TTL means

1. two-transistor logic.
2. transistor-transistor logic.
3. transistor-transceiver latch.
4. three-transistor logic.

42. The CMOS series that is pin compatible with the TTL family is the

1. 5400 series.
2. 7400 series.
3. 74C00 series.
4. 4000 series.

43. The difference between VOH and VIH voltages is known as

1. output differential.
2. input level.
3. input margin.
4. noise margin.

44. The input transistor (Q 1) of a TTL gate acts like

1. an AND gate.
2. an OR gate.
3. a NAND gate.
4. a NOR gate.

45. The input transistor on a TTL circuit is unusual in that it has

1. no base
2. multiple emitters.
3. multiple bases.
4. no collector

46. The lower transistor of a totem-pole output is OFF when the gate output is

1. LOW.
2. over driven.
3. HIGH.
4. malfunctioning.

47. The lower transistor of a totem-pole output is saturated when the gate output is

1. malfunctioning.
2. over driven.
3. HIGH.
4. LOW.

48. The major advantage of CMOS logic circuits over TTL is

1. lower propagation delay.
2. much higher propagation delay.
3. very low power consumption.
4. the ability to produce several output voltage levels.

49. The major advantage of TTL logic circuits over CMOS is

1. more modern design.
2. very low power consumption.
3. lower propagation delay.
4. the ability to output higher voltages.

50. The maximum current for a HIGH output on a standard TTL gate is

1. -1 µA.
2. -10 mA.
3. -10 µA.
4. -400 µA.