Parallel Processing MCQ Multiple Choice Questions Answers | Quiz for Practice

Q: 1. Data hazards occur when

Correct Answer is: Pipeline changes the order of read/write access to operands

Q: 4. For a given FINITE number of instructions to be executed, which architecture of the processor provides for a faster execution ?

Correct Answer is: Super-scalar

Q: 5. For a RS flip-flop constructed with NAND gates and input R=1 and s=1 the state is

Correct Answer is: Unused state

Q: 7. How does the number of transistors per chip increase according to Moores law?

Correct Answer is: Exponentially

Q: 14. In immediate addressing the operand is placed

Correct Answer is: after opcode in the instruction

Parallel Processing Multiple Choice Questions (MCQs) are essential practice tools for students and exam aspirants. These questions help you test your understanding and prepare effectively for various assessments.

About Parallel Processing MCQ Questions

Parallel Processing MCQs cover a wide range of topics including parallel architectures, algorithms, and synchronization techniques. These questions are designed to deepen your understanding of how multiple processors work together to solve complex computational problems efficiently.

Why Practice Parallel Processing Objective Questions?

Practicing Parallel Processing MCQs offers several benefits. They help you prepare for school and college exams, enhance your readiness for competitive exams, and boost your confidence for technical interviews. Regular practice ensures that you have a solid grasp of the fundamental and advanced concepts in parallel processing.

Who Should Use These MCQs?

Students preparing for school or college exams
Competitive exam aspirants
Candidates preparing for interviews

Parallel Processing MCQ Questions for Practice

1. Data hazards occur when

Greater performance loss
Pipeline changes the order of read/write access to operands
Some functional unit is not fully pipelined
Machine size is limited

2. During the execution of the instructions, a copy of the instructions is placed in the

Register
RAM
System heap
Cache

3. Dynamic RAMs are best suited to

slow system
large system
one bit system
none of the above

4. For a given FINITE number of instructions to be executed, which architecture of the processor provides for a faster execution ?

ISA
ANSA
Super-scalar
All of the above

5. For a RS flip-flop constructed with NAND gates and input R=1 and s=1 the state is

Memory state
Set state
Reset state
Unused state

6. From where interrupts are generated?A

Central processing unitB
Memory chipsC
RegistersD
I/O devices

7. How does the number of transistors per chip increase according to Moores law?

Quadratically
Linearly
Cubicly
Exponentially

8. How many address lines are needed to address each memory location in a 2048X 4 memory chip?

9. How many bits do you think will be adequate to encode individual character in Devnagari script

10. In a single byte how many bits will be there?

11. In a system with a 16 bit address bus, what is the maximum number of 1K byte memory devices it could contain

16
64
256
65536

12. In CISC architecture most of the complex instructions are stored in

Register
Diodes
CMOS
Transistors

13. In daisy-chaining priority method, all the devices that can request an interrupt are connected in

parallel
serial
random
none of the above

14. In immediate addressing the operand is placed

in the CPU register
after opcode in the instruction
in the memory
in the stack