VLSI Design MCQ Multiple Choice Questions Answers - Page 2 for Practice

31. The maximum output voltage recognized as a LOW by a TTL gate is

32. The minimum input voltage recognized as a HIGH by a TTL gate is

33. The minimum output voltage recognized as a HIGH by a TTL gate is

34. The noise margin for a standard TTL gate is

35. The number of gates that can be connected to a single output without exceeding the current ratings of the gate is called

36. The original CMOS line of circuits is the

37. The output current capability for a HIGH output condition is called a(n)

38. The output current for a LOW output is called a(n)

39. The output stage of a TTL gate is a special design called a(n)

40. The primary advantage of ECL over TTL is that ECL integrated circuits have

41. The propagation delay of standard TTL gates is approximately

42. The standard 74XX TTL IC family was originally developed in the

43. The time it takes for a square wave to go from 10% to 90% of its voltage level is called

44. The time it takes for a square wave to go from 90% to 10% of its voltage level is called

45. The time it takes for an input signal to pass through internal circuitry and generate the appropriate output effect is known as

46. The unused input for a NOR gate should be tied to

47. The upper transistor of a totem-pole output is OFF when the gate output is

48. The upper transistor of a totem-pole output is saturated when the gate output is

49. Typical TTL HIGH level output voltage is

50. Typical TTL LOW level output voltage is

51. Unused inputs on TTL, AND, and NAND gates

52. What advantage does the 74HXX series device have over standard TTL?

53. What advantage does the 74LSXX series device have over standard TTL?

54. What advantage does the 74LXX series device have over standard TTL?

55. What advantage does the 74SXX series device have over standard TTL?

56. When a CMOS gate output connects to a TTL gate, which circuit is needed?

57. When a TTL gate output connects to a CMOS gate, what must be added to the circuit?

58. When interfacing CMOS to TTL what potential problem must be overcome?

59. When the outputs of several open-collector TTL gates are connected together, the gate outputs

60. When the outputs of several standard TTL gates are connected together, the gate outputs


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