Correct Answer is: Multiple copies of same data are available at each level of hierarchy.

Correct Answer is: Executable and Linkable Format

Multiple copies of same data are available at each level of hierarchy.

Multiple copies of different data are not available at each level of hierarchy.

Single copy of data is available at only one level of hierarchy.

Multiple copies of different data are available at only one level of hierarchy.

ARM Processor Architecture MCQ Multiple Choice Questions Answers for Practice

Q: 3. ..........is the concept in which a process memory is copied into the main memory from the secondary memory according to the requirement.

Correct Answer is: Demand paging

Q: 4. “Write Back” cache write policy is more efficient in a system where

Correct Answer is: Number of writes are more than reads

Q: 5. A band limited signal can be reconstructed exactly if it is sampled at a rate at least

Correct Answer is: Twice the maximum frequency

Q: 6. A bus cycle request that transfers to or from an address which is unrelated to the address used in the preceding cycle is called a

Correct Answer is: Non-Sequential Cycle

Q: 7. A CPU wrote „register content‟ into the memory in a Big-endian mode. When the same content is read back from the memory into a register, the CPU reads it in Little-endian mode.

Correct Answer is: The new content in the register will be different from what was written.

Q: 9. A Page Table contains information on the page including

Correct Answer is: All of the above

Q: 10. A process is thrashing if

Correct Answer is: it is spending more time paging management than executing

Q: 11. A scheduling algorithm can use either..........priority or..........priority.

Correct Answer is: static, dynamic

Q: 12. A virtual memory system uses „First In First Out‟ (FIFO) page replacement policy and allocates a fixed number of frames to a process. Consider the following tatements:P: Increasing the number of page frames allocated to a process sometimes increases the page fault rateQ: Some programs do not exhibit locality of reference which of the following is TRUE?

Correct Answer is: P is false but Q is true

Q: 15. Cache design elements are

Correct Answer is: All of the above

1. Fixed instruction length is a feature of one of the following architecture.

CISC
RISC
X86
None of the above

2. Which of the following register in ARM7 is used to point to the location of currently executing instruction in a program?

3. ..........is the concept in which a process memory is copied into the main memory from the secondary memory according to the requirement.

Paging
Demand paging
Segmentation
Swapping

4. “Write Back” cache write policy is more efficient in a system where

Number of writes are more than reads
Number of reads are more than writes
Does not depend on the number of reads and writes
None of the above

5. A band limited signal can be reconstructed exactly if it is sampled at a rate at least

Maximum frequency
Twice the maximum frequency
Thrice the maximum frequency
All of the above

6. A bus cycle request that transfers to or from an address which is unrelated to the address used in the preceding cycle is called a

Sequential Cycle
Internal Cycle
Non-Sequential Cycle
Coprocessor Register Transfer Cycle

7. A CPU wrote „register content‟ into the memory in a Big-endian mode. When the same content is read back from the memory into a register, the CPU reads it in Little-endian mode.

The new content in the register will be different from what was written.
The content will be the same.
The content may be same or different.
Endianness need not be the same while reading and writing the contents into/from the memory.

8. A data processing instruction where PC(R15)is written into takes the following cycles for execution:

1S
1S+I
2S+1N
2S+1N+1I

9. A Page Table contains information on the page including

Base address of each page in physical memory
Page read/write permissions
Page was written into or not
All of the above

10. A process is thrashing if

it is spending more time paging management than executing
it is spending less time paging than executing
page fault occurs very infrequently
swapping could not take place

11. A scheduling algorithm can use either..........priority or..........priority.

static, still
static, dynamic
live, dead
None of the above

12. A virtual memory system uses „First In First Out‟ (FIFO) page replacement policy and allocates a fixed number of frames to a process. Consider the following tatements:
P: Increasing the number of page frames allocated to a process sometimes increases the page fault rate
Q: Some programs do not exhibit locality of reference which of the following is TRUE?

Both P and Q are true, and Q is the reason for P
Both P and Q are true, but Q is not the reason for P
P is false but Q is true
Both P and Q are false

13. An instruction that is used to move data from an ARM Register to a Status Register (CPSR or SPSR) is called

14. By default DMA is not a

Master
Slave
Clock
All of the above

15. Cache design elements are

Block size
Cache size
Mapping functions
All of the above

16. Cache memory acts between

CPU and Main Memory
CPU and FPU
MMU and Hard Disk
None of these

17. Choose the correct order for default memory map

RW->RO->ZI
ZI->RO->RW
RO->RW->ZI
RO->ZI->RW

18. Coherence means

Multiple copies of different data are not available at each level of hierarchy.
Multiple copies of same data are available at each level of hierarchy.
Single copy of data is available at only one level of hierarchy.
Multiple copies of different data are available at only one level of hierarchy.

19. Consider a four bit ALU which does four bit arithmetic. When the following four bit numbers are added, what is the status of NZCV flags? 1101 + 1011

NZCV = 0111
NZCV = 1000
NZCV = 1001
NZCV = 1010

20. Control signals can be categorized by the pipeline stage that uses them. Which one of the following signal could be used in the Execution stage of an instruction?

MemRead
RegWrite
ALUop
PCsrc

21. ELF means

External Library Format
Executable and Linkable Format
Exclusive Loadable Format
None of the above

22. Equivalent of Rd = NOT(Rm) this operation is performed by which instruction

23. Evaluate the following statements and select the appropriate answer given from the choices below.
I. Von Neumann Architecture shares common memory for Data and Instructions
II. Harvard Architecture has separate physical memories for Data and Instructions

Only I is true
Only II is true
Both I and II are true
None of them is true

24. Evaluate the following statements
I. R13 is traditionally used as the stack pointer and stores the head of the stack in the current processor mode
II. R14 is the link register where the core puts the return address on executing a subroutine
III. R15 is the program counter and contains the address of the next instruction to be fetched

All the options are true
I and II are true
II and III are true
I and III are true

25. Exponent and fraction values for a denormalized number are

0, 0
0 < E < Max, Any bit pattern
All 1?s, Any bit pattern
0, Any non-zero bit pattern

26. Frequency of sampling is called

Sampling rate
Quantization
Modulation
All of the above

27. How do Direct Addressing Mode instructions compare with respect to the Indirect Addressing Mode instructions?

Faster
Slower
No difference
None of the above

28. How many bits are required to specify the Register operands in anARM7 instruction?

32 bits
16 bits
4 bits
2 bits

29. I2C master features:

Programmable I2C address detection
Clock generation
Stop bit detection
All of the above

30. If an instruction takes 3 cycles for execution, then how many cycles are needed for executing4 instructions of the same type in a sequence using a 3-stage pipeline? Assume that there are no interrupts or exceptions while executing them.

12 cycles
6 cycles
9 cycles
4 cycles

ARM Processor Architecture MCQs are essential practice tools for students and exam aspirants. These multiple-choice questions help solidify your understanding of ARM architecture, making you well-prepared for assessments and real-world applications.

About ARM Processor Architecture MCQ Questions

ARM Processor Architecture MCQs cover a wide range of topics, from the basics of ARM architecture to advanced concepts like instruction sets, pipeline operations, and system design. These questions are designed to test your knowledge and ensure you have a comprehensive understanding of ARM processors.

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Practicing ARM Processor Architecture MCQs offers several benefits. It helps you prepare for school and college exams, enhances your performance in competitive exams, and boosts your confidence for technical interviews. Regular practice also aids in revising key concepts and identifying areas that need more attention.

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