ARM Processor Architecture MCQ Multiple Choice Questions

Q: 1. The memory blocks in Main Memory are mapped on to the cache blocks with the help of

Correct Answer is: None of the above

Q: 4. The multi-layer architecture acts as a crossbar switch between............in a AMBA 3 AHB

Correct Answer is: None of the above

Q: 5. The priority of a process will.........if the scheduler assigns it a static priority.

Correct Answer is: None of the above

Q: 6. The two I2C signals are..........and............

Correct Answer is: Parallel address, Parallel clock

Q: 7. Thumb-2 technology enhances the 16 bit Thumb instruction set with

Correct Answer is: None of the above

Q: 8. Using only two instructions, add a 64-bit integer contained in R2 and R3 to another 64-bit integer contained in R0 and R1, and place the result in R4 and R5.

Correct Answer is: ADD r4, r0, r2 ; ADCS r5, r1, r3 ;

Q: 9. Vector Floating Point (VFP) architecture is power efficient because of reduction in...........and...........

Correct Answer is: All of the above

Q: 10. Vector Floating Point (VFP) architecture provides............floating point architectures.

Correct Answer is: None of the above

Q: 12. What are the contents of R1 and R2after MVNR1 R2 are executed, assume R2 is 0x01010101

Correct Answer is: i) R2 = 0x01100110 ii) R1 = 0x01010101

Q: 13. What is inter-process communication?

Correct Answer is: None of the above

ARM Processor Architecture MCQs are essential practice tools for students and exam aspirants. These multiple-choice questions help solidify your understanding of ARM architecture, making you well-prepared for assessments and real-world applications.

About ARM Processor Architecture MCQ Questions

ARM Processor Architecture MCQs cover a wide range of topics, from the basics of ARM architecture to advanced concepts like instruction sets, pipeline operations, and system design. These questions are designed to test your knowledge and ensure you have a comprehensive understanding of ARM processors.

Why Practice ARM Processor Architecture Objective Questions?

Practicing ARM Processor Architecture MCQs offers several benefits. It helps you prepare for school and college exams, enhances your performance in competitive exams, and boosts your confidence for technical interviews. Regular practice also aids in revising key concepts and identifying areas that need more attention.

Who Should Use These MCQs?

ARM Processor Architecture MCQ Questions for Practice

1. The memory blocks in Main Memory are mapped on to the cache blocks with the help of

Hash functions
Vectors
Mapping functions
None of the above

2. The memory which is used to store acopy of data or instructions stored in larger memories, inside the CPU is called

Level 1 cache
MMU
Registers
TLB

3. The method of mapping the consecutive memory blocks to consecutive cache blocks is called

Set associative
Associative
Direct
Indirect

4. The multi-layer architecture acts as a crossbar switch between............in a AMBA 3 AHB

Master and slave
Master and master
Slave and slave
None of the above

5. The priority of a process will.........if the scheduler assigns it a static priority.

change
remain unchanged
depend on the operating system
None of the above

6. The two I2C signals are..........and............

Serial data, serial clock
Serial select, serial access
Serial address, parallel data
Parallel address, Parallel clock

7. Thumb-2 technology enhances the 16 bit Thumb instruction set with

Intermixing of 32 bits and 16 bits instructions
Only 32 bits instructions
Only 16 bits instructions
None of the above

8. Using only two instructions, add a 64-bit integer contained in R2 and R3 to another 64-bit integer contained in R0 and R1, and place the result in R4 and R5.

ADD r4, r0, r2 ; ADC r5, r1, r3 ;
ADDS r4, r0, r2 ; ADCS r5, r1, r3 ;
ADD r4, r0, r2 ; ADD r5, r1, r3 ;
ADD r4, r0, r2 ; ADCS r5, r1, r3 ;

9. Vector Floating Point (VFP) architecture is power efficient because of reduction in...........and...........

Instruction bandwidth and Data hazard checking
Instruction bandwidth and pipelining
Data Hazard checking and pipelining
All of the above

10. Vector Floating Point (VFP) architecture provides............floating point architectures.

Single precision
Double precision
Both a and b
None of the above

11. Vector processor architecture falls under the following computer architecture

SISD
MIMD
SIMD
MISD

12. What are the contents of R1 and R2after MVNR1 R2 are executed, assume R2 is 0x01010101

i) R2 = 0x01010101 ii) R1 = 0x01010101
i) R2 = 0x01010101 ii) R1 = 0x10101010
i) R2 = 0x10101010 ii) R1 = 0x01011101
i) R2 = 0x01100110 ii) R1 = 0x01010101

13. What is inter-process communication?

Communication within the process
Communication between two processes
Communication between two threads of same process
None of the above

14. When a global variable may be modified by an exception handler, it should be declared as:

Constant
Static
Dynamic
Volatile

15. When a page is selected for replacement, and its modify bit is set :

the page is clean
the page has been modified since it was read in from the disk
the page is dirty
a and b

16. When a transfer is required the APB bus moves into the

hold state
setup state
Rising state
None

17. When semi-hosting is executed, the debug agent

Suspends program execution
Continues program execution
Both a and b
None of the above

18. When the number of stages in a pipeline increases from 3 to 5, then the

Throughput reduces
Latency reduces
Throughput and latency increases
Throughput increases and latency reduces

19. When the processor is executing simple data processing instructions, the pipeline enables one instruction to be completed every clock cycle, this is also called as

Throughput
Latency
Execution
None of the above

20. Which among the following data processing instructions does not use the barrel shifter?

ADD R2, R5, R4
MOV R5, R4, LSL #2
MOV r5, R4, LSR #2
MOV r5, R4, ROR #2

21. Which of the following instruction ignores Operand1

22. Which of the following is not one of the source files of a linker to form an executable?

.obj
.lef
.so
.lib

23. Which of the following is the reason that the Least Recently Used (LRU) algorithm is usually not used as a page replacement algorithm?

Other practical schemes such as MIN do a better job
LRU requires knowledge of the future to work correctly
LRU is too inefficient to implement in practice
The Clock algorithm always outperforms LRU

24. Which of the following may not be on the APB bus

USART
RAM
Keypad
Timer module

25. Which of the following processors belong to Reduced Instruction Set Computers (RISC family)?

ARM
AVR
MIPS
All of the above

26. Which of the following statements are true with respect to pipelining.
I. Pipelining is an implementation technique whereby multiple instructions are overlapped in execution. It is not visible to the programmer
II. Each step is called a pipe stage or pipe segment
III. Pipeline machine cycle is the time required to move an instruction one step down the pipeline

All are true
I and III are true
II and III are true
None of them are true

27. Which of the following statements are true
I. In Little endian mode it is easier to determine a sign of the number
II. Little endian mode is easier for addition and multiplication of multi-precision numbers
III. Big endian mode is easier to divide two numbers
IV. Big endian mode is easier to compare two numbers

I & II are true
III & IV are true
I & III are true and II and IV are false
I & II are false and III and IV are true

28. Write Through technique is used in one of the following to write the data back.

Virtual memory
Main memory
Auxiliary memory
Cache memory

29. Fixed instruction length is a feature of one of the following architecture.

CISC
RISC
X86
None of the above

ARM Processor Architecture MCQ Multiple Choice Questions for Practice

About ARM Processor Architecture MCQ Questions

Why Practice ARM Processor Architecture Objective Questions?

Who Should Use These MCQs?

ARM Processor Architecture MCQ Questions for Practice

1. The memory blocks in Main Memory are mapped on to the cache blocks with the help of

2. The memory which is used to store acopy of data or instructions stored in larger memories, inside the CPU is called

3. The method of mapping the consecutive memory blocks to consecutive cache blocks is called

4. The multi-layer architecture acts as a crossbar switch between............in a AMBA 3 AHB

5. The priority of a process will.........if the scheduler assigns it a static priority.

6. The two I2C signals are..........and............

7. Thumb-2 technology enhances the 16 bit Thumb instruction set with

8. Using only two instructions, add a 64-bit integer contained in R2 and R3 to another 64-bit integer contained in R0 and R1, and place the result in R4 and R5.

9. Vector Floating Point (VFP) architecture is power efficient because of reduction in...........and...........

10. Vector Floating Point (VFP) architecture provides............floating point architectures.

11. Vector processor architecture falls under the following computer architecture

12. What are the contents of R1 and R2after MVNR1 R2 are executed, assume R2 is 0x01010101

13. What is inter-process communication?

14. When a global variable may be modified by an exception handler, it should be declared as:

15. When a page is selected for replacement, and its modify bit is set :

16. When a transfer is required the APB bus moves into the

17. When semi-hosting is executed, the debug agent

18. When the number of stages in a pipeline increases from 3 to 5, then the

19. When the processor is executing simple data processing instructions, the pipeline enables one instruction to be completed every clock cycle, this is also called as

20. Which among the following data processing instructions does not use the barrel shifter?

21. Which of the following instruction ignores Operand1

22. Which of the following is not one of the source files of a linker to form an executable?

23. Which of the following is the reason that the Least Recently Used (LRU) algorithm is usually not used as a page replacement algorithm?

24. Which of the following may not be on the APB bus

25. Which of the following processors belong to Reduced Instruction Set Computers (RISC family)?

28. Write Through technique is used in one of the following to write the data back.

29. Fixed instruction length is a feature of one of the following architecture.

30. Which of the following register in ARM7 is used to point to the location of currently executing instruction in a program?

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ARM Processor Architecture MCQ Multiple Choice Questions for Practice

About ARM Processor Architecture MCQ Questions

Why Practice ARM Processor Architecture Objective Questions?

Who Should Use These MCQs?

ARM Processor Architecture MCQ Questions for Practice

1. The memory blocks in Main Memory are mapped on to the cache blocks with the help of

2. The memory which is used to store acopy of data or instructions stored in larger memories, inside the CPU is called

3. The method of mapping the consecutive memory blocks to consecutive cache blocks is called

4. The multi-layer architecture acts as a crossbar switch between............in a AMBA 3 AHB

5. The priority of a process will.........if the scheduler assigns it a static priority.

6. The two I2C signals are..........and............

7. Thumb-2 technology enhances the 16 bit Thumb instruction set with

8. Using only two instructions, add a 64-bit integer contained in R2 and R3 to another 64-bit integer contained in R0 and R1, and place the result in R4 and R5.

9. Vector Floating Point (VFP) architecture is power efficient because of reduction in...........and...........

10. Vector Floating Point (VFP) architecture provides............floating point architectures.

11. Vector processor architecture falls under the following computer architecture

12. What are the contents of R1 and R2after MVNR1 R2 are executed, assume R2 is 0x01010101

13. What is inter-process communication?

14. When a global variable may be modified by an exception handler, it should be declared as:

15. When a page is selected for replacement, and its modify bit is set :

16. When a transfer is required the APB bus moves into the

17. When semi-hosting is executed, the debug agent

18. When the number of stages in a pipeline increases from 3 to 5, then the

19. When the processor is executing simple data processing instructions, the pipeline enables one instruction to be completed every clock cycle, this is also called as

20. Which among the following data processing instructions does not use the barrel shifter?

21. Which of the following instruction ignores Operand1

22. Which of the following is not one of the source files of a linker to form an executable?

23. Which of the following is the reason that the Least Recently Used (LRU) algorithm is usually not used as a page replacement algorithm?

24. Which of the following may not be on the APB bus

25. Which of the following processors belong to Reduced Instruction Set Computers (RISC family)?

28. Write Through technique is used in one of the following to write the data back.

29. Fixed instruction length is a feature of one of the following architecture.

30. Which of the following register in ARM7 is used to point to the location of currently executing instruction in a program?

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