ARM Processor Architecture MCQ Multiple Choice Questions

Q: 61. State whether the following statement is either true or false. Reset vector is the location of the first instruction executed by the processor when power is applie

Correct Answer is: This instruction branches to the initialization code.

Q: 62. State whether the following statement is either true or false. The set associative map technique combines the benefits of the direct and associative mapping techniques.

Correct Answer is: True Statement

Q: 63. State whether the following statement is either true or false. We can represent any number in more than one normalized notation.

Correct Answer is: False Statement

Q: 65. The amount of time required to read a block of data from a disk into memory is composed of seek time, rotational latency, and transfer time. Rotational latency refers to

Correct Answer is: the time it takes for the platter to make a full rotation

Q: 68. The idea of cache memory exploits the following property of programs

Correct Answer is: Principle of locality

Q: 69. The L1 cache is typically split into.........and...........cache for the pipelined system

Correct Answer is: Instruction, Data

Q: 70. The Logical Instructions are: ORR, EOR, TEQ, AND, TST, BIC, MOV, MVN Why is the V flag unaffected by the logical data processing instructions?

Correct Answer is: V flag is relevant only when an Arithmetic operation is performed

Q: 71. The main advantage of multiple bus organization over the single bus is

Correct Answer is: Reduction in the number of cycles for execution

Q: 72. The MCLK speed can be reduced to allow access to

Correct Answer is: Slower peripherals

Q: 73. The memory blocks in Main Memory are mapped on to the cache blocks with the help of

Correct Answer is: Mapping functions

61. State whether the following statement is either true or false. Reset vector is the location of the first instruction executed by the processor when power is applie

This instruction branches to the initialization code.
True Statement
False Statement

62. State whether the following statement is either true or false. The set associative map technique combines the benefits of the direct and associative mapping techniques.

True Statement
False Statement

63. State whether the following statement is either true or false. We can represent any number in more than one normalized notation.

True Statement
False Statement

64. Status of Z flag after the execution of CMP instruction given below, when R0 = 12; R9 = 12; is CMP R0, R9

Z = 1
Z = 0
Same as previous value
None of the above

65. The amount of time required to read a block of data from a disk into memory is composed of seek time, rotational latency, and transfer time. Rotational latency refers to

the time it takes for the platter to make a full rotation
the time it takes for the read-write head to move into position over the appropriate track
the time it takes for the platter to rotate the correct sector under the head
none of the above

66. The average time required to reach a storage location in memory and obtain its contents is called

Latency time
Access time
Turnaround time
Response time

67. The fastest data access is provided using

Caches
DRAM?s
SRAM?s
Registers

68. The idea of cache memory exploits the following property of programs

Principle of locality
on the heuristic 90-10 rule
on the fact that references generally tend to be farther
all of the above

69. The L1 cache is typically split into.........and...........cache for the pipelined system

Instruction, Data
Instruction, Instruction
Data, Data
All of the above

70. The Logical Instructions are: ORR, EOR, TEQ, AND, TST, BIC, MOV, MVN Why is the V flag unaffected by the logical data processing instructions?

Since V flag and C flag are always the same after any logical operations
Because it will delay the execution of logical operations
V flag is relevant only when an Arithmetic operation is performed
None of the above

71. The main advantage of multiple bus organization over the single bus is

Reduction in the number of cycles for execution
Increase in size of the register
Better connectivity
None of the above

72. The MCLK speed can be reduced to allow access to

Faster peripherals
Slower peripherals
CPU
All of the above

73. The memory blocks in Main Memory are mapped on to the cache blocks with the help of

Hash functions
Vectors
Mapping functions
None of the above

74. The memory which is used to store acopy of data or instructions stored in larger memories, inside the CPU is called

Level 1 cache
MMU
Registers
TLB

75. The method of mapping the consecutive memory blocks to consecutive cache blocks is called

Set associative
Associative
Direct
Indirect

76. The multi-layer architecture acts as a crossbar switch between............in a AMBA 3 AHB

Master and slave
Master and master
Slave and slave
None of the above

77. The priority of a process will.........if the scheduler assigns it a static priority.

change
remain unchanged
depend on the operating system
None of the above

78. The two I2C signals are..........and............

Serial data, serial clock
Serial select, serial access
Serial address, parallel data
Parallel address, Parallel clock

79. Thumb-2 technology enhances the 16 bit Thumb instruction set with

Intermixing of 32 bits and 16 bits instructions
Only 32 bits instructions
Only 16 bits instructions
None of the above

80. Using only two instructions, add a 64-bit integer contained in R2 and R3 to another 64-bit integer contained in R0 and R1, and place the result in R4 and R5.

ADD r4, r0, r2 ; ADC r5, r1, r3 ;
ADDS r4, r0, r2 ; ADCS r5, r1, r3 ;
ADD r4, r0, r2 ; ADD r5, r1, r3 ;
ADD r4, r0, r2 ; ADCS r5, r1, r3 ;

81. Vector Floating Point (VFP) architecture is power efficient because of reduction in...........and...........

Instruction bandwidth and Data hazard checking
Instruction bandwidth and pipelining
Data Hazard checking and pipelining
All of the above

82. Vector Floating Point (VFP) architecture provides............floating point architectures.

Single precision
Double precision
Both a and b
None of the above

83. Vector processor architecture falls under the following computer architecture

SISD
MIMD
SIMD
MISD

84. What are the contents of R1 and R2after MVNR1 R2 are executed, assume R2 is 0x01010101

i) R2 = 0x01010101 ii) R1 = 0x01010101
i) R2 = 0x01010101 ii) R1 = 0x10101010
i) R2 = 0x10101010 ii) R1 = 0x01011101
i) R2 = 0x01100110 ii) R1 = 0x01010101

85. What is inter-process communication?

Communication within the process
Communication between two processes
Communication between two threads of same process
None of the above

86. When a global variable may be modified by an exception handler, it should be declared as:

Constant
Static
Dynamic
Volatile

87. When a page is selected for replacement, and its modify bit is set :

the page is clean
the page has been modified since it was read in from the disk
the page is dirty
a and b

88. When a transfer is required the APB bus moves into the

hold state
setup state
Rising state
None

89. When semi-hosting is executed, the debug agent

Suspends program execution
Continues program execution
Both a and b
None of the above

90. When the number of stages in a pipeline increases from 3 to 5, then the

Throughput reduces
Latency reduces
Throughput and latency increases
Throughput increases and latency reduces

ARM Processor Architecture MCQ Multiple Choice Questions - Page 3 for Practice

61. State whether the following statement is either true or false. Reset vector is the location of the first instruction executed by the processor when power is applie

62. State whether the following statement is either true or false. The set associative map technique combines the benefits of the direct and associative mapping techniques.

63. State whether the following statement is either true or false. We can represent any number in more than one normalized notation.

64. Status of Z flag after the execution of CMP instruction given below, when R0 = 12; R9 = 12; is CMP R0, R9

65. The amount of time required to read a block of data from a disk into memory is composed of seek time, rotational latency, and transfer time. Rotational latency refers to

66. The average time required to reach a storage location in memory and obtain its contents is called

67. The fastest data access is provided using

68. The idea of cache memory exploits the following property of programs

69. The L1 cache is typically split into.........and...........cache for the pipelined system

70. The Logical Instructions are: ORR, EOR, TEQ, AND, TST, BIC, MOV, MVN Why is the V flag unaffected by the logical data processing instructions?

71. The main advantage of multiple bus organization over the single bus is

72. The MCLK speed can be reduced to allow access to

73. The memory blocks in Main Memory are mapped on to the cache blocks with the help of

74. The memory which is used to store acopy of data or instructions stored in larger memories, inside the CPU is called

75. The method of mapping the consecutive memory blocks to consecutive cache blocks is called

76. The multi-layer architecture acts as a crossbar switch between............in a AMBA 3 AHB

77. The priority of a process will.........if the scheduler assigns it a static priority.

78. The two I2C signals are..........and............

79. Thumb-2 technology enhances the 16 bit Thumb instruction set with

80. Using only two instructions, add a 64-bit integer contained in R2 and R3 to another 64-bit integer contained in R0 and R1, and place the result in R4 and R5.

81. Vector Floating Point (VFP) architecture is power efficient because of reduction in...........and...........

82. Vector Floating Point (VFP) architecture provides............floating point architectures.

83. Vector processor architecture falls under the following computer architecture

84. What are the contents of R1 and R2after MVNR1 R2 are executed, assume R2 is 0x01010101

85. What is inter-process communication?

86. When a global variable may be modified by an exception handler, it should be declared as:

87. When a page is selected for replacement, and its modify bit is set :

88. When a transfer is required the APB bus moves into the

89. When semi-hosting is executed, the debug agent

90. When the number of stages in a pipeline increases from 3 to 5, then the

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ARM Processor Architecture MCQ Multiple Choice Questions - Page 3 for Practice

61. State whether the following statement is either true or false. Reset vector is the location of the first instruction executed by the processor when power is applie

62. State whether the following statement is either true or false. The set associative map technique combines the benefits of the direct and associative mapping techniques.

63. State whether the following statement is either true or false. We can represent any number in more than one normalized notation.

64. Status of Z flag after the execution of CMP instruction given below, when R0 = 12; R9 = 12; is CMP R0, R9

65. The amount of time required to read a block of data from a disk into memory is composed of seek time, rotational latency, and transfer time. Rotational latency refers to

66. The average time required to reach a storage location in memory and obtain its contents is called

67. The fastest data access is provided using

68. The idea of cache memory exploits the following property of programs

69. The L1 cache is typically split into.........and...........cache for the pipelined system

70. The Logical Instructions are: ORR, EOR, TEQ, AND, TST, BIC, MOV, MVN Why is the V flag unaffected by the logical data processing instructions?

71. The main advantage of multiple bus organization over the single bus is

72. The MCLK speed can be reduced to allow access to

73. The memory blocks in Main Memory are mapped on to the cache blocks with the help of

74. The memory which is used to store acopy of data or instructions stored in larger memories, inside the CPU is called

75. The method of mapping the consecutive memory blocks to consecutive cache blocks is called

76. The multi-layer architecture acts as a crossbar switch between............in a AMBA 3 AHB

77. The priority of a process will.........if the scheduler assigns it a static priority.

78. The two I2C signals are..........and............

79. Thumb-2 technology enhances the 16 bit Thumb instruction set with

80. Using only two instructions, add a 64-bit integer contained in R2 and R3 to another 64-bit integer contained in R0 and R1, and place the result in R4 and R5.

81. Vector Floating Point (VFP) architecture is power efficient because of reduction in...........and...........

82. Vector Floating Point (VFP) architecture provides............floating point architectures.

83. Vector processor architecture falls under the following computer architecture

84. What are the contents of R1 and R2after MVNR1 R2 are executed, assume R2 is 0x01010101

85. What is inter-process communication?

86. When a global variable may be modified by an exception handler, it should be declared as:

87. When a page is selected for replacement, and its modify bit is set :

88. When a transfer is required the APB bus moves into the

89. When semi-hosting is executed, the debug agent

90. When the number of stages in a pipeline increases from 3 to 5, then the

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