ARM Processor Architecture MCQs Quiz Multiple Choice Questions & Answers Page 2

51. Evaluate the following statements and select the appropriate answer given from the choices below.
I. Von Neumann Architecture shares common memory for Data and Instructions
II. Harvard Architecture has separate physical memories for Data and Instructions

1. Only I is true
2. Only II is true
3. Both I and II are true
4. None of them is true

52. Evaluate the following statements
I. R13 is traditionally used as the stack pointer and stores the head of the stack in the current processor mode
II. R14 is the link register where the core puts the return address on executing a subroutine
III. R15 is the program counter and contains the address of the next instruction to be fetched

1. All the options are true
2. I and II are true
3. II and III are true
4. I and III are true

53. Exponent and fraction values for a denormalized number are

1. 0, 0
2. 0 < E < Max, Any bit pattern
3. All 1?s, Any bit pattern
4. 0, Any non-zero bit pattern

54. Frequency of sampling is called

1. Sampling rate
2. Quantization
3. Modulation
4. All of the above

55. How do Direct Addressing Mode instructions compare with respect to the Indirect Addressing Mode instructions?

1. Faster
2. Slower
3. No difference
4. None of the above

56. How many bits are required to specify the Register operands in anARM7 instruction?

1. 32 bits
2. 16 bits
3. 4 bits
4. 2 bits

57. I2C master features:

1. Programmable I2C address detection
2. Clock generation
3. Stop bit detection
4. All of the above

58. If an instruction takes 3 cycles for execution, then how many cycles are needed for executing4 instructions of the same type in a sequence using a 3-stage pipeline? Assume that there are no interrupts or exceptions while executing them.

1. 12 cycles
2. 6 cycles
3. 9 cycles
4. 4 cycles

59. If the access time of a cache is 1nS, and the access time of a main memory is 15nS, assuming that the Cache hit rate is 0.9 and the total number of accesses are 100; then the average access times of the access with cache and without cache will be..........and...........

1. 250 nS and 1500 nS
2. 250mS and 150 nS
3. 25 nS and 1500nS
4. 250mS and 1500mS

60. If the initial register contents of R0, R1 and R2 were; R0= 0x00000000 , R1= 0x02040608 , R2= 0x10305070 . Assume R0 is the result register, after one of the operations below was performed on R1 and R2, which has been modified to R0 = 0x12345678 What was the operation performed on the contents of R2 and R1?

1. AND
2. ORR
3. BIC
4. MUL

61. If the Most Significant Byte (MS) is stored first while ordering byte values for storing data in memory, it is called as

1. Big-endian
2. Little-endian
3. Big- and Little-endian
4. None of them

62. If Vector Floating Point (VPF) has to handle 8-single precision numbers, VPF architecture must have..........processing elements that work in parallel.

1. 8
2. 16
3. 24
4. 1

63. In a 32- bit IEEE 754 notation, biased value of exponent value ranges from

1. -126 to 127
2. 0 to 127
3. -126 to 0
4. None of the above

64. In an Operating System, each process has its own

1. address space and global variables
2. open files
3. pending alarms, signals and signal handlers
4. all of the above

65. In the ARM Nomenclature ARMxTDMI, D and M stand for

1. Debug and Fast Multiplier units are present
2. Division and Multiplier units are present
3. Debugger and Multiplier units are not present
4. Division and Multiplier units are not present

66. In the memory hierarchy, as the speed of memory access increases the memory size

1. Increases
2. Decreases
3. Both
4. None of the above

67. Instruction used to multiply R5 contents by R4 and to store the result into R6 is called

1. MUL R6, R5, LSL #2
2. MUL R6, R5, R4
3. MUL R6, R5, LSR #2
4. None of the above

68. Instruction used to Test equality of two 32-bit values in ARM7 is called

1. TEQ
2. TST
3. EOR
4. None of the above

69. Main advantage of the PWM is that

1. Power loss in the switching devices is very high
2. Power loss in the switching devices is very low
3. No power loss in switching devices
4. None of the above

70. Memory management technique in which the OS stores and retrieves data from secondary storage for use in main memory is called

1. Fragmentation
2. Paging
3. Mapping
4. None of the above

71. Memory unit accessed by its content is called

1. Read only memory
2. Programmable Memory
3. Virtual Memory
4. Associative Memory

72. Minimum possible denormalized number representation is possible with single precision IEEE 754 format is

1. 2^-126
2. 2^-127
3. 2^-149
4. 2^-128

73. MRC, MCR are the

1. Co-processor register transfer instructions
2. Thumb instructions
3. Both a and b
4. Shift instructions

74. Operating System maintains the page table for

1. Each data element
2. Each instruction
3. Each address
4. Each process

75. R1 = 0b1111 , R2 = 0b0101 , BIC R0, R1, R2

1. R0 = 0b1010
2. R0 = 0b1111
3. R0 = 0b0101
4. R0 = 0b1100

76. Run time mapping from virtual to physical address is done by

1. Memory Management Unit
2. CPU
3. PCI
4. None of the above

77. Serial Peripheral Interface bus allows

1. Half/full
2. Synchronous
3. Serial communication with external devices
4. All of the above

78. Size of L1 cache compared to that of L2 cache in a system is

1. Higher
2. Lower
3. Same
4. None of the above

79. Stack is a form of

1. Last In First Out (LIFO)
2. First In First Out (FIFO)
3. Both a and b
4. None of the above

80. State whether the following statement is either true or false. A high performance bus can be connected to a low performance bus without bridge.

1. True Statement
2. False Statement

81. State whether the following statement is either true or false. Address of any data in cache memory always refers to the address of the data in Main Memory and not the address within the cache.

1. True Statement
2. False Statement

82. State whether the following statement is either true or false. Full technical specifications of the target hardware, memory map of the target system may not be available during SW development in most of the cases.

1. True Statement
2. False Statement

83. State whether the following statement is either true or false. In a multilevel system cache system, the L2 cache may contain data that is not found in L1 cache.

1. True Statement
2. False Statement

84. State whether the following statement is either true or false. In a system with Unified cache, access to data in the cache may impact program execution as well.

1. True Statement
2. False Statement

85. State whether the following statement is either true or false. In direct mapping, the presence of the block in memory is checked with the help of block field.

1. True Statement
2. False Statement

86. State whether the following statement is either true or false. Increasing the block size of cache memory is likely to increase performance primarily because programs exhibit spatial locality.

1. True Statement
2. False Statement

87. State whether the following statement is either true or false. Interrupt signal can stop the execution of an assembly instruction in the middle while it is being executed.

1. False Statement
2. True Statement

88. State whether the following statement is either true or false. Mantissa and exponent will improve the range and precision respectively.

1. True Statement
2. False Statement

89. State whether the following statement is either true or false. Reset vector is the location of the first instruction executed by the processor when power is applie

1. This instruction branches to the initialization code.
2. True Statement
3. False Statement

90. State whether the following statement is either true or false. The set associative map technique combines the benefits of the direct and associative mapping techniques.

1. True Statement
2. False Statement

91. State whether the following statement is either true or false. We can represent any number in more than one normalized notation.

1. True Statement
2. False Statement

92. Status of Z flag after the execution of CMP instruction given below, when R0 = 12; R9 = 12; is CMP R0, R9

1. Z = 1
2. Z = 0
3. Same as previous value
4. None of the above

93. The amount of time required to read a block of data from a disk into memory is composed of seek time, rotational latency, and transfer time. Rotational latency refers to

1. the time it takes for the platter to make a full rotation
2. the time it takes for the read-write head to move into position over the appropriate track
3. the time it takes for the platter to rotate the correct sector under the head
4. none of the above

94. The average time required to reach a storage location in memory and obtain its contents is called

1. Latency time
2. Access time
3. Turnaround time
4. Response time

95. The fastest data access is provided using

1. Caches
2. DRAM?s
3. SRAM?s
4. Registers

96. The idea of cache memory exploits the following property of programs

1. Principle of locality
2. on the heuristic 90-10 rule
3. on the fact that references generally tend to be farther
4. all of the above

97. The L1 cache is typically split into.........and...........cache for the pipelined system

1. Instruction, Data
2. Instruction, Instruction
3. Data, Data
4. All of the above

98. The Logical Instructions are: ORR, EOR, TEQ, AND, TST, BIC, MOV, MVN Why is the V flag unaffected by the logical data processing instructions?

1. Since V flag and C flag are always the same after any logical operations
2. Because it will delay the execution of logical operations
3. V flag is relevant only when an Arithmetic operation is performed
4. None of the above

99. The main advantage of multiple bus organization over the single bus is

1. Reduction in the number of cycles for execution
2. Increase in size of the register
3. Better connectivity
4. None of the above

100. The MCLK speed can be reduced to allow access to

1. Faster peripherals
2. Slower peripherals
3. CPU
4. All of the above