ARM Processor Architecture Objective Question and Answer
ARM Processor Architecture MCQ Multiple Choice Questions - Page 2 for Practice
31. If the access time of a cache is 1nS, and the access time of a main memory is 15nS, assuming that the Cache hit rate is 0.9 and the total number of accesses are 100; then the average access times of the access with cache and without cache will be..........and...........
Correct Answer is: 250 nS and 1500 nS
32. If the initial register contents of R0, R1 and R2 were; R0= 0x00000000 , R1= 0x02040608 , R2= 0x10305070 . Assume R0 is the result register, after one of the operations below was performed on R1 and R2, which has been modified to R0 = 0x12345678 What was the operation performed on the contents of R2 and R1?
Correct Answer is: ORR
33. If the Most Significant Byte (MS) is stored first while ordering byte values for storing data in memory, it is called as
Correct Answer is: Big-endian
34. If Vector Floating Point (VPF) has to handle 8-single precision numbers, VPF architecture must have..........processing elements that work in parallel.
Correct Answer is: 8
35. In a 32- bit IEEE 754 notation, biased value of exponent value ranges from
Correct Answer is: -126 to 127
36. In an Operating System, each process has its own
Correct Answer is: all of the above
37. In the ARM Nomenclature ARMxTDMI, D and M stand for
Correct Answer is: Debug and Fast Multiplier units are present
38. In the memory hierarchy, as the speed of memory access increases the memory size
Correct Answer is: Decreases
39. Instruction used to multiply R5 contents by R4 and to store the result into R6 is called
Correct Answer is: MUL R6, R5, R4
40. Instruction used to Test equality of two 32-bit values in ARM7 is called
Correct Answer is: TEQ
41. Main advantage of the PWM is that
Correct Answer is: Power loss in the switching devices is very low
42. Memory management technique in which the OS stores and retrieves data from secondary storage for use in main memory is called
Correct Answer is: Paging
43. Memory unit accessed by its content is called
Correct Answer is: Associative Memory
44. Minimum possible denormalized number representation is possible with single precision IEEE 754 format is
Correct Answer is: 2-149
45. MRC, MCR are the
Correct Answer is: Co-processor register transfer instructions
46. Operating System maintains the page table for
Correct Answer is: Each process
47. R1 = 0b1111 , R2 = 0b0101 , BIC R0, R1, R2
Correct Answer is: R0 = 0b1010
48. Run time mapping from virtual to physical address is done by
Correct Answer is: Memory Management Unit
49. Serial Peripheral Interface bus allows
Correct Answer is: All of the above
50. Size of L1 cache compared to that of L2 cache in a system is
Correct Answer is: Lower
51. Stack is a form of
Correct Answer is: Last In First Out (LIFO)
52. State whether the following statement is either true or false. A high performance bus can be connected to a low performance bus without bridge.
Correct Answer is: False Statement
53. State whether the following statement is either true or false. Address of any data in cache memory always refers to the address of the data in Main Memory and not the address within the cache.
Correct Answer is: True Statement
54. State whether the following statement is either true or false. Full technical specifications of the target hardware, memory map of the target system may not be available during SW development in most of the cases.
Correct Answer is: True Statement
55. State whether the following statement is either true or false. In a multilevel system cache system, the L2 cache may contain data that is not found in L1 cache.
Correct Answer is: True Statement
56. State whether the following statement is either true or false. In a system with Unified cache, access to data in the cache may impact program execution as well.
Correct Answer is: True Statement
57. State whether the following statement is either true or false. In direct mapping, the presence of the block in memory is checked with the help of block field.
Correct Answer is: False Statement
58. State whether the following statement is either true or false. Increasing the block size of cache memory is likely to increase performance primarily because programs exhibit spatial locality.
Correct Answer is: True Statement
59. State whether the following statement is either true or false. Interrupt signal can stop the execution of an assembly instruction in the middle while it is being executed.
Correct Answer is: False Statement
60. State whether the following statement is either true or false. Mantissa and exponent will improve the range and precision respectively.
