ARM Processor Architecture Objective Question and Answer
ARM Processor Architecture MCQ Multiple Choice Questions - Page 2 for Practice
31. ..........is the concept in which a process memory is copied into the main memory from the secondary memory according to the requirement.
Correct Answer is: Demand paging
32. “Write Back” cache write policy is more efficient in a system where
Correct Answer is: Number of writes are more than reads
33. A band limited signal can be reconstructed exactly if it is sampled at a rate at least
Correct Answer is: Twice the maximum frequency
34. A bus cycle request that transfers to or from an address which is unrelated to the address used in the preceding cycle is called a
Correct Answer is: Non-Sequential Cycle
35. A CPU wrote „register content‟ into the memory in a Big-endian mode. When the same content is read back from the memory into a register, the CPU reads it in Little-endian mode.
Correct Answer is: The new content in the register will be different from what was written.
36. A data processing instruction where PC(R15)is written into takes the following cycles for execution:
Correct Answer is: 2S+1N
37. A Page Table contains information on the page including
Correct Answer is: All of the above
38. A process is thrashing if
Correct Answer is: it is spending more time paging management than executing
39. A scheduling algorithm can use either..........priority or..........priority.
Correct Answer is: static, dynamic
40. A virtual memory system uses „First In First Out‟ (FIFO) page replacement policy and allocates a fixed number of frames to a process. Consider the following tatements: P: Increasing the number of page frames allocated to a process sometimes increases the page fault rate Q: Some programs do not exhibit locality of reference which of the following is TRUE?
Correct Answer is: P is false but Q is true
41. An instruction that is used to move data from an ARM Register to a Status Register (CPSR or SPSR) is called
Correct Answer is: MSR
42. By default DMA is not a
Correct Answer is: Master
43. Cache design elements are
Correct Answer is: All of the above
44. Cache memory acts between
Correct Answer is: CPU and Main Memory
45. Choose the correct order for default memory map
Correct Answer is: RO->RW->ZI
46. Coherence means
Correct Answer is: Multiple copies of same data are available at each level of hierarchy.
47. Consider a four bit ALU which does four bit arithmetic. When the following four bit numbers are added, what is the status of NZCV flags? 1101 + 1011
Correct Answer is: NZCV = 1010
48. Control signals can be categorized by the pipeline stage that uses them. Which one of the following signal could be used in the Execution stage of an instruction?
Correct Answer is: ALUop
49. ELF means
Correct Answer is: Executable and Linkable Format
50. Equivalent of Rd = NOT(Rm) this operation is performed by which instruction
Correct Answer is: MVN
51. Evaluate the following statements and select the appropriate answer given from the choices below. I. Von Neumann Architecture shares common memory for Data and Instructions II. Harvard Architecture has separate physical memories for Data and Instructions
Correct Answer is: Both I and II are true
52. Evaluate the following statements I. R13 is traditionally used as the stack pointer and stores the head of the stack in the current processor mode II. R14 is the link register where the core puts the return address on executing a subroutine III. R15 is the program counter and contains the address of the next instruction to be fetched
Correct Answer is: All the options are true
53. Exponent and fraction values for a denormalized number are
Correct Answer is: 0, Any non-zero bit pattern
54. Frequency of sampling is called
Correct Answer is: Sampling rate
55. How do Direct Addressing Mode instructions compare with respect to the Indirect Addressing Mode instructions?
Correct Answer is: Faster
56. How many bits are required to specify the Register operands in anARM7 instruction?
Correct Answer is: 4 bits
57. I2C master features:
Correct Answer is: Clock generation
58. If an instruction takes 3 cycles for execution, then how many cycles are needed for executing4 instructions of the same type in a sequence using a 3-stage pipeline? Assume that there are no interrupts or exceptions while executing them.
Correct Answer is: 6 cycles
59. If the access time of a cache is 1nS, and the access time of a main memory is 15nS, assuming that the Cache hit rate is 0.9 and the total number of accesses are 100; then the average access times of the access with cache and without cache will be..........and...........
Correct Answer is: 250 nS and 1500 nS
60. If the initial register contents of R0, R1 and R2 were; R0= 0x00000000 , R1= 0x02040608 , R2= 0x10305070 . Assume R0 is the result register, after one of the operations below was performed on R1 and R2, which has been modified to R0 = 0x12345678 What was the operation performed on the contents of R2 and R1?
