ARM Processor Architecture MCQs Quiz Multiple Choice Questions & Answers Page 2

ARM Processor Architecture MCQs questions answers

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ARM Processor Architecture Questions with Answers

51. Evaluate the following statements and select the appropriate answer given from the choices below.
I. Von Neumann Architecture shares common memory for Data and Instructions
II. Harvard Architecture has separate physical memories for Data and Instructions

52. Evaluate the following statements
I. R13 is traditionally used as the stack pointer and stores the head of the stack in the current processor mode
II. R14 is the link register where the core puts the return address on executing a subroutine
III. R15 is the program counter and contains the address of the next instruction to be fetched

53. Exponent and fraction values for a denormalized number are

54. Frequency of sampling is called

55. How do Direct Addressing Mode instructions compare with respect to the Indirect Addressing Mode instructions?

56. How many bits are required to specify the Register operands in anARM7 instruction?

57. I2C master features:

58. If an instruction takes 3 cycles for execution, then how many cycles are needed for executing4 instructions of the same type in a sequence using a 3-stage pipeline? Assume that there are no interrupts or exceptions while executing them.

59. If the access time of a cache is 1nS, and the access time of a main memory is 15nS, assuming that the Cache hit rate is 0.9 and the total number of accesses are 100; then the average access times of the access with cache and without cache will be..........and...........

60. If the initial register contents of R0, R1 and R2 were; R0= 0x00000000 , R1= 0x02040608 , R2= 0x10305070 . Assume R0 is the result register, after one of the operations below was performed on R1 and R2, which has been modified to R0 = 0x12345678 What was the operation performed on the contents of R2 and R1?

61. If the Most Significant Byte (MS) is stored first while ordering byte values for storing data in memory, it is called as

62. If Vector Floating Point (VPF) has to handle 8-single precision numbers, VPF architecture must have..........processing elements that work in parallel.

63. In a 32- bit IEEE 754 notation, biased value of exponent value ranges from

64. In an Operating System, each process has its own

65. In the ARM Nomenclature ARMxTDMI, D and M stand for

66. In the memory hierarchy, as the speed of memory access increases the memory size

67. Instruction used to multiply R5 contents by R4 and to store the result into R6 is called

68. Instruction used to Test equality of two 32-bit values in ARM7 is called

69. Main advantage of the PWM is that

70. Memory management technique in which the OS stores and retrieves data from secondary storage for use in main memory is called

71. Memory unit accessed by its content is called

72. Minimum possible denormalized number representation is possible with single precision IEEE 754 format is

73. MRC, MCR are the

74. Operating System maintains the page table for

75. R1 = 0b1111 , R2 = 0b0101 , BIC R0, R1, R2

76. Run time mapping from virtual to physical address is done by

77. Serial Peripheral Interface bus allows

78. Size of L1 cache compared to that of L2 cache in a system is

79. Stack is a form of

80. State whether the following statement is either true or false. A high performance bus can be connected to a low performance bus without bridge.

81. State whether the following statement is either true or false. Address of any data in cache memory always refers to the address of the data in Main Memory and not the address within the cache.

82. State whether the following statement is either true or false. Full technical specifications of the target hardware, memory map of the target system may not be available during SW development in most of the cases.

83. State whether the following statement is either true or false. In a multilevel system cache system, the L2 cache may contain data that is not found in L1 cache.

84. State whether the following statement is either true or false. In a system with Unified cache, access to data in the cache may impact program execution as well.

85. State whether the following statement is either true or false. In direct mapping, the presence of the block in memory is checked with the help of block field.

86. State whether the following statement is either true or false. Increasing the block size of cache memory is likely to increase performance primarily because programs exhibit spatial locality.

87. State whether the following statement is either true or false. Interrupt signal can stop the execution of an assembly instruction in the middle while it is being executed.

88. State whether the following statement is either true or false. Mantissa and exponent will improve the range and precision respectively.

89. State whether the following statement is either true or false. Reset vector is the location of the first instruction executed by the processor when power is applie

90. State whether the following statement is either true or false. The set associative map technique combines the benefits of the direct and associative mapping techniques.

91. State whether the following statement is either true or false. We can represent any number in more than one normalized notation.

92. Status of Z flag after the execution of CMP instruction given below, when R0 = 12; R9 = 12; is CMP R0, R9

93. The amount of time required to read a block of data from a disk into memory is composed of seek time, rotational latency, and transfer time. Rotational latency refers to

94. The average time required to reach a storage location in memory and obtain its contents is called

95. The fastest data access is provided using

96. The idea of cache memory exploits the following property of programs

97. The L1 cache is typically split into.........and...........cache for the pipelined system

98. The Logical Instructions are: ORR, EOR, TEQ, AND, TST, BIC, MOV, MVN Why is the V flag unaffected by the logical data processing instructions?

99. The main advantage of multiple bus organization over the single bus is

100. The MCLK speed can be reduced to allow access to


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