Digital Electronics Trivia Quizzes for Practice

61. The output of a gated S-R flip-flop changes only if the:

1. flip-flop is set
2. control input data has changed
3. flip-flop is reset
4. input data has no change

62. When both inputs of a J-K flip-flop cycle, the output will:

1. be invalid
2. not change
3. change
4. toggle

63. What is the significance of the J and K terminals on the J-K flip-flop?

1. There is no known significance in their designations
2. The J represents "jump," which is how the Q output reacts whenever the clock goes HIGH and the J input is also HIGH
3. The letters represent the initials of Johnson and King, the co-inventors of the J-K flip-flop
4. All of the other letters of the alphabet are already in use

64. How is a J-K flip-flop made to toggle?

1. J = 0, K = 0
2. J = 1, K = 0
3. J = 0, K = 1
4. J = 1, K = 1

65. A J-K flip-flop is in a "no change" condition when ________

1. J = 1, K = 1
2. J = 1, K = 0
3. J = 0, K = 1
4. J = 0, K = 0

66. A correct output is achieved from a master-slave J-K flip-flop only if its inputs are stable while the:

1. clock is LOW
2. slave is transferring
3. flip-flop is reset
4. clock is HIGH

67. A J-K flip-flop with J = 1 and K = 1 has a 20 kHz clock input. The Q output is ________

1. constantly LOW
2. constantly HIGH
3. a 20 kHz square wave
4. a 10 kHz square wave

68. The toggle condition in a master-slave J-K flip-flop means that Q and will switch to their ________ state(s) at the ________

1. opposite, active clock edge
2. inverted, positive clock edge
3. quiescent, negative clock edge
4. reset, synchronous clock edge

69. What is the significance of the J and K terminals on the J-K flip-flop?

1. There is no known significance in their designations
2. The J represents "jump," which is how the Q output reacts whenever the clock goes high and the J input is also HIGH
3. The letters were chosen in honor of Jack Kilby, the inventory of the integrated circuit
4. All of the other letters of the alphabet are already in use

70. On a J-K flip-flop, when is the flip-flop in a hold condition?

1. J = 0, K = 0
2. J = 1, K = 0
3. J = 0, K = 1
4. J = 1, K = 1

71. Two J-K flip-flops with their J-K inputs tied HIGH are cascaded to be used as counters. After four input clock pulses, the binary count is ________?

1. 11
2. 11
3. 1