Digital Electronics MCQs Quiz Multiple Choice Questions & Answers Page 2

Digital Electronics MCQs questions answers


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Digital Electronics Questions with Answers

51. One example of the use of an S-R flip-flop is as a(n)

52. If both inputs of an S-R NAND latch are LOW, what will happen to the output?

53. The truth table for an S-R flip-flop has how many VALID entries?

54. What is one disadvantage of an S-R flip-flop?

55. How can the cross-coupled NAND flip-flop be made to have active-HIGH S-R inputs?

56. On a positive edge-triggered S-R flip-flop, the outputs reflect the input condition when ________

57. What is the hold condition of a flip-flop?

58. If an active-HIGH S-R latch has a 0 on the S input and a 1 on the R input and then the R input goes to 0, the latch will be ________?

59. What is one disadvantage of an S-R flip-flop?

60. The terminal count of a 3-bit binary counter in the DOWN mode is ________?

61. The output of a gated S-R flip-flop changes only if the:

62. When both inputs of a J-K flip-flop cycle, the output will:

63. What is the significance of the J and K terminals on the J-K flip-flop?

64. How is a J-K flip-flop made to toggle?

65. A J-K flip-flop is in a "no change" condition when ________

66. A correct output is achieved from a master-slave J-K flip-flop only if its inputs are stable while the:

67. A J-K flip-flop with J = 1 and K = 1 has a 20 kHz clock input. The Q output is ________

68. The toggle condition in a master-slave J-K flip-flop means that Q and will switch to their ________ state(s) at the ________

69. What is the significance of the J and K terminals on the J-K flip-flop?

70. On a J-K flip-flop, when is the flip-flop in a hold condition?

71. Two J-K flip-flops with their J-K inputs tied HIGH are cascaded to be used as counters. After four input clock pulses, the binary count is ________?

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