Digital Electronics MCQ Multiple Choice Questions - Page 2 for Practice

Digital Electronics MCQ Questions for Practice

31. The output of an OR gate is LOW when ________.

32. The Ex-NOR is sometimes called the ________.

33. A logic circuit that provides a HIGH output if one input or the other input, but not both, is HIGH, is a(n):

34. The output of an AND gate with three inputs, A, B, and C, is HIGH when ________.

35. When used with an IC, what does the term "QUAD" indicate?

36. The output of an OR gate with three inputs, A, B, and C, is LOW when ________.

37. Which of the following logical operations is represented by the + sign in Boolean algebra?

38. Output will be a LOW for any case when one or more inputs are zero for a(n):

39. A basic multiplexer principle can be demonstrated through the use of a:

40. One multiplexer can take the place of:

41. The inputs/outputs of an analog multiplexer/demultiplexer are:

42. One application of a digital multiplexer is to facilitate:

43. How many select lines would be required for an 8-line-to-1-line multiplexer?

44. Which of the following is correct for a gated D-type flip-flop?

45. Which of the following describes the operation of a positive edge-triggered D-type flip-flop?

46. Which of the following is correct for a D latch?

47. A D flip-flop utilizing a PGT clock is in the CLEAR state. Which of the following input actions will cause it to change states?

48. A positive edge-triggered D flip-flop will store a 1 when ________

49. If an input is activated by a signal transition, it is ________

50. A basic S-R flip-flop can be constructed by cross-coupling which basic logic gates?

51. One example of the use of an S-R flip-flop is as a(n)

52. If both inputs of an S-R NAND latch are LOW, what will happen to the output?

53. The truth table for an S-R flip-flop has how many VALID entries?

54. What is one disadvantage of an S-R flip-flop?

55. How can the cross-coupled NAND flip-flop be made to have active-HIGH S-R inputs?

56. On a positive edge-triggered S-R flip-flop, the outputs reflect the input condition when ________

57. What is the hold condition of a flip-flop?

58. If an active-HIGH S-R latch has a 0 on the S input and a 1 on the R input and then the R input goes to 0, the latch will be ________?

59. What is one disadvantage of an S-R flip-flop?

60. The terminal count of a 3-bit binary counter in the DOWN mode is ________?

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Multiple Choice Questions and Answers on Digital Electronics

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