51. The maximum current for a LOW output on a standard TTL gate is
52. The maximum input voltage recognized as a LOW by a TTL gate is
53. The maximum output voltage recognized as a LOW by a TTL gate is
54. The minimum input voltage recognized as a HIGH by a TTL gate is
55. The minimum output voltage recognized as a HIGH by a TTL gate is
56. The noise margin for a standard TTL gate is
57. The number of gates that can be connected to a single output without exceeding the current ratings of the gate is called
58. The original CMOS line of circuits is the
59. The output current capability for a HIGH output condition is called a(n)
60. The output current for a LOW output is called a(n)
61. The output stage of a TTL gate is a special design called a(n)
62. The primary advantage of ECL over TTL is that ECL integrated circuits have
63. The propagation delay of standard TTL gates is approximately
64. The standard 74XX TTL IC family was originally developed in the
65. The time it takes for a square wave to go from 10% to 90% of its voltage level is called
66. The time it takes for a square wave to go from 90% to 10% of its voltage level is called
67. The time it takes for an input signal to pass through internal circuitry and generate the appropriate output effect is known as
68. The unused input for a NOR gate should be tied to
69. The upper transistor of a totem-pole output is OFF when the gate output is
70. The upper transistor of a totem-pole output is saturated when the gate output is
71. Typical TTL HIGH level output voltage is
72. Typical TTL LOW level output voltage is
73. Unused inputs on TTL, AND, and NAND gates
74. What advantage does the 74HXX series device have over standard TTL?
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