VLSI Design MCQ Questions and Answers Quiz

71. Which of the following output levels would be a valid HIGH for a TTL gate?

  1. 3.0 V
  2. 2.6 V
  3. 5.1 V
  4. All are valid.

72. Which of the following output levels would not be a valid LOW for a TTL gate?

  1. 0.3 V
  2. 0.5 V
  3. 0.2 V
  4. All are valid.

73. Which potential problem must be overcome when interfacing TTL to CMOS?

  1. The HIGH output voltage may be too low.
  2. The LOW output voltage may be too high.
  3. The HIGH output voltage may be too high.
  4. The output current may not be sufficient.

74. Which specialized device distinguishes the 74LSXX circuits from standard 74XX circuits?

  1. a Schottky diode
  2. a CMOS transistor
  3. a multiemitter transistor
  4. totem-pole output transistor
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