VLSI Design MCQ Questions and Answers Quiz

31. The maximum output voltage recognized as a LOW by a TTL gate is

  1. 2.0 V.
  2. 0.8 V.
  3. 2.4 V.
  4. 0.4 V. 3

32. The minimum input voltage recognized as a HIGH by a TTL gate is

  1. 0.8 V.
  2. 2.4 V.
  3. 2.0 V.
  4. 5.0 V.

33. The minimum output voltage recognized as a HIGH by a TTL gate is

  1. 0.8 V.
  2. 2.4 V.
  3. 5.0 V.
  4. 2.0 V.

34. The noise margin for a standard TTL gate is

  1. 1.0 V.
  2. 0.4 V.
  3. 1.4 V.
  4. 0.8 V.

35. The number of gates that can be connected to a single output without exceeding the current ratings of the gate is called

  1. dissipation.
  2. propagation.
  3. fan-out.
  4. SSI.

36. The original CMOS line of circuits is the

  1. 5400 series.
  2. 4000 series.
  3. 74C00 series.
  4. 74HCOO series.

37. The output current capability for a HIGH output condition is called a(n)

  1. source current.
  2. exit current.
  3. sink current.
  4. fan-out.

38. The output current for a LOW output is called a(n)

  1. exit current.
  2. sink current.
  3. ground current.
  4. fan-out.

39. The output stage of a TTL gate is a special design called a(n)

  1. totem-pole.
  2. DIP.
  3. MSI.
  4. multiemitter.

40. The primary advantage of ECL over TTL is that ECL integrated circuits have

  1. very low power dissipation.
  2. low noise margins.
  3. very short propagation delay times.
  4. both A and C
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