Parallel Processing MCQ Quiz - Multiple Choice Questions & Answers Page 4

31. In daisy-chaining priority method, all the devices that can request an interrupt are connected in

1. parallel
2. serial
3. random
4. none of the above

32. In immediate addressing the operand is placed

1. in the CPU register
2. after opcode in the instruction
3. in the memory
4. in the stack

33. Instruction pipelining has minimum stages

1. 4
2. 2
3. 3
4. 6

34. Intel 8080 microprocessor has an instruction set of 91 instruction. The opcode to implement this instruction set should be at least

1. 3 bit long
2. 5 bit long
3. 7 bit long
4. 9 bit long

35. Intel Pentium CPU is a

1. RISC based
2. CISC based
3. Both of the above
4. None of the above

36. Interrupts which are initiated by an instruction are

1. internal
2. external
3. hardware
4. Software

37. Itanium processor: Which hazard can be circumvented by register rotation?

1. Control hazards
2. Data hazards
3. Structural hazards
4. None

38. Memory access in RISC architecture is limited to instructions

1. CALL and RET
2. PUSH and POP
3. STA and LDA
4. MOV and JMP

39. Memory address refers to the successive memory words and the machine is called as

1. word addressable
2. byte addressable
3. bit addressable
4. Terra byte addressable

40. Micro instructions are stored in

1. computer memory
2. primary storage
3. secondary storage
4. control memory