Parallel Processing MCQs Quiz Multiple Choice Questions & Answers

1. Data hazards occur when

1. Some functional unit is not fully pipelined
2. Machine size is limited
3. Greater performance loss
4. Pipeline changes the order of read/write access to operands

2. During the execution of the instructions, a copy of the instructions is placed in the

1. System heap
2. Cache
3. Register
4. RAM

3. Dynamic RAMs are best suited to

1. one bit system
2. none of the above
3. slow system
4. large system

4. For a given FINITE number of instructions to be executed, which architecture of the processor provides for a faster execution ?

1. Super-scalar
2. All of the above
3. ISA
4. ANSA

5. For a RS flip-flop constructed with NAND gates and input R=1 and s=1 the state is

1. Reset state
2. Unused state
3. Memory state
4. Set state

6. From where interrupts are generated?A

1. RegistersD
2. I/O devices
3. Central processing unitB
4. Memory chipsC

7. How does the number of transistors per chip increase according to Moores law?

1. Cubicly
2. Exponentially
3. Quadratically
4. Linearly

8. How many address lines are needed to address each memory location in a 2048X 4 memory chip?

1. 8
2. 12
3. 10
4. 11

9. How many bits do you think will be adequate to encode individual character in Devnagari script

1. 64
2. 10
3. 12
4. 16

10. In a single byte how many bits will be there?

1. 4
2. 32
3. 8
4. 16

11. In a system with a 16 bit address bus, what is the maximum number of 1K byte memory devices it could contain

1. 256
2. 65536
3. 16
4. 64

12. In CISC architecture most of the complex instructions are stored in

1. CMOS
2. Transistors
3. Register
4. Diodes

13. In daisy-chaining priority method, all the devices that can request an interrupt are connected in

1. random
2. none of the above
3. parallel
4. serial

14. In immediate addressing the operand is placed

1. in the memory
2. in the stack
3. in the CPU register
4. after opcode in the instruction

15. Instruction pipelining has minimum stages

1. 3
2. 6
3. 4
4. 2

16. Intel 8080 microprocessor has an instruction set of 91 instruction. The opcode to implement this instruction set should be at least

1. 7 bit long
2. 9 bit long
3. 3 bit long
4. 5 bit long

17. Intel Pentium CPU is a

1. Both of the above
2. None of the above
3. RISC based
4. CISC based

18. Interrupts which are initiated by an instruction are

1. hardware
2. Software
3. internal
4. external

19. Itanium processor: Which hazard can be circumvented by register rotation?

1. Structural hazards
2. None
3. Control hazards
4. Data hazards

20. Memory access in RISC architecture is limited to instructions

1. STA and LDA
2. MOV and JMP
3. CALL and RET
4. PUSH and POP

21. Memory address refers to the successive memory words and the machine is called as

1. bit addressable
2. Terra byte addressable
3. word addressable
4. byte addressable

22. Micro instructions are stored in

1. secondary storage
2. control memory
3. computer memory
4. primary storage

23. Out of the following which is not a CISC machine.

1. Intel 80486
2. Motorola A567
3. IBM 370/168
4. VAX 11/780

24. Parallel processing may occur

1. both[A] and [B]
2. none of the above
3. in the instruction stream
4. in the data stream

25. Parallel programs: Which speedup could be achieved according to Amdahls law for infinite number of processors if 5% of a program is sequential and the remaining part is ideally parallel?

1. 20
2. 50
3. Infinite speedup
4. 5

26. PC Program Counter is also called

1. data counter
2. file pointer
3. instruction pointer
4. memory pointer

27. Pipeline implement

1. fetch operand
2. calculate operand
3. fetch instruction
4. decode instruction

28. Pipe-lining is a unique feature of

1. ISA
2. IANA
3. RISC
4. CISC

29. Pipelining strategy is called implement

1. instruction decoding
2. instruction manipulation
3. instruction execution
4. instruction prefetch

30. Processors of all computers, whether micro, mini or mainframe must have

1. Control unit
2. All of above
3. ALU
4. Primary Storage

31. SPEC stands for,

1. System Performance Evaluation Corporation.
2. Standard Processing Enhancement Corporation.
3. Standard Performance Evaluation Code.
4. System Processing Enhancing Code.

32. Systems that do not have parallel processing capabilities are

1. MIMD
2. All of the above
3. SISD
4. SIMD

33. Te devices connected to a microprocessor can use the data bus:

1. only when it’s sending or receiving data
2. when the microprocessor is reset
3. all the time
4. at regular interval of time

34. The 16- bit registers in 8085 is

1. stack pointer and program counter
2. all of the above
3. general purpose register
4. accumulator

35. The access time of memory is ............... the time required for performing any single CPU operation.

1. Negligible than
2. Same as
3. Longer than
4. Shorter than

36. The advantage of RISC processor over CISC processor is that

1. Less number of registers accommodate in chip
2. Parallel execution capabilities
3. The hardware architecture is simpler
4. An instruction can be executed in one cycle

37. The average number of steps taken to execute the set of instructions can be made to be less than one by following

1. Super-scaling
2. Sequential
3. ISA
4. Pipe-lining

38. The CISC stands for

1. Computer Indexed Set Components
2. Complex Instruction set computer
3. Computer Instruction Set Compliment
4. Complete Instruction Set Compliment

39. The clock rate of the processor can be improved by,

1. By using overclocking method
2. All of the above
3. Improving the IC technology of the logic circuits
4. Reducing the amount of processing done in one step

40. The computer architecture aimed at reducing the time of execution of instructions is

1. ISA
2. ANNA
3. CISC
4. RISC

41. The concept of pipelining is most effective in improving performance if the tasks being performed in different stages :

1. require different amount of time with time difference between any two tasks being same
2. require different amount with time difference between any two tasks being different
3. require different amount of time
4. require about the same amount of time

42. The cost of a parallel processing is primarily determined by :

1. Circuit Complexity
2. None of the above
3. Time Complexity
4. Switching Complexity

43. The expression delayed load is used in context of

1. pipelining
2. none of the above
3. processor-printer communication
4. memory-monitor communication

44. The iconic feature of the RISC machine among the following are

1. Having a branch delay slot
2. All of the above
3. Reduced number of addressing modes
4. Increased memory size

45. The maximum integer which can be stored on a 8 bit accumulator is

1. 255
2. 224
3. 112
4. 200

46. The most common addressing techiniques employed by a CPU is

1. indirect
2. all of the above
3. immediate
4. direct

47. The output of a gate is low when at least one of its input is low . It is true forA

1. NAND gateD
2. NOR gate
3. AND gateB
4. OR gateC

48. The RISC processor has a more complicated design than CISC.

1. True Statement
2. False Statement

49. The Sun micro systems processors usually follow..................architecture.

1. ULTRA SPARC
2. RISC
3. CISC
4. ISA

50. The ultimate goal of a compiler is to,

1. Be versatile.
2. Be able to detect even the smallest of errors.
3. Reduce the clock cycles for a programming task.
4. Reduce the size of the object code.