Digital Electronics MCQs Quiz Multiple Choice Questions & Answers

1. What are the symbols used to represent digits in the binary number system?

1. 0 through 8
2. 1,2
3. 0,1
4. 0,1,2

2. The sum of 11101 + 10111 equals ________.

1. 100001
2. 100100
3. 110011
4. 110100

3. A binary number's value changes most drastically when the ________ is changed.

1. MSB
2. Duty cycle
3. Frequency
4. LSB

4. The binary number 111 is equal to the decimal number ________.

1. 7
2. 12
3. 2
4. 5

5. Hexadecimal letters A through F are used for decimal equivalent values from:

1. 9 through 14
2. 11 through 17
3. 1 through 6
4. 10 through 15

6. Digital electronics is based on the ________ numbering system.

1. Octal
2. Hexadecimal
3. Decimal
4. Binary

7. The 1's complement of 10011101 is ________.

1. 1100001
2. 1100011
3. 1100010
4. 10011110

8. When using the repeated division by 2 method of converting from decimal to binary, one must write the first remainder as the:

1. LSB, provided the final remainder is used to replace the original LSB, which is then moved to the MSB position.
2. MSB
3. MSB, provided the following sequence of remainders are written in descending order until the final remainder is achieved.
4. LSB

9. The decimal value for E

1. 14
2. 12
3. 12
4. 10

10. Solve this binary problem: 01110010 – 01001000

1. 1110010
2. 111100
3. 11010
4. 101010

11. Which of the following is the most widely used alphanumeric code for computer input and output?

1. Parity
2. EBCDIC
3. Gray
4. ASCII

12. Which is typically the longest?

1. Nibble
2. Word
3. Bit
4. Byte

13. The BCD number for decimal 347 is ________.

1. 0011 0100 0001
2. 1100 1011 0110
3. 1100 1011 1000
4. 0011 0100 0111

14. The sum of the two BCD numbers, 0011 + 0011, is ________.

1. 11
2. 1100
3. 110
4. 111

15. Convert the binary number 1100 to Gray code.

1. 1001
2. 1100
3. 11
4. 1010

16. Convert binary 111111110010 to hexadecimal.

1. FD2
2. FF2
3. EE2
4. 2FE

17. When used with an IC, what does the term "QUAD" indicate?

1. 6 circuits
2. 8 circuits1
3. 2 circuits
4. 4 circuits

18. Convert decimal 64 to binary.

1. 110110
2. 1001000
3. 1010010
4. 1000000

19. Convert Hexadecimal 8B3F to binary

1. 1.0100011111E+15
2. 1.00010110011E+15
3. 75647
4. 10010

20. Convert the Gray code 1011 to binary.

1. 1101
2. 1111
3. 1011
4. 1010

21. Add the binary number 1011 and 1101

1. 11011
2. 11111
3. 11000
4. 11001

22. Add the binary numbers 1010.1101 and 101.01

1. 10010.0001
2. 10010.0011
3. 10000.0001
4. 10000.0011

23. Which one of the following will give the sum of full-adder as output?

1. Three bit parity comparator
2. Three bit counter
3. Three input majority circuit
4. Three bit parity checker

24. Boolean logic is concerned with

1. Hexadecimal number
2. Octal number
3. Binary number
4. Decimal number

25. Perform the subtraction of 1011 and 0110

1. 101
2. 111
3. 1100
4. 100

26. Perform the subtraction of 1110 and 1001

1. 111
2. 110
3. 1100
4. 101

27. Which one of the following is equivalent to AND-OR realization?

1. NOR-NOR realization
2. NAND-NAND realization
3. NAND-NOR realization
4. NOR-NAND realization

28. Full adder can be changed into full subtractor circuit by adding one

1. OR Gate
2. Inverter
3. NOR Gate
4. AND Gate

29. The output of an AND gate is LOW ________.

1. When any input is HIGH
2. When all inputs are HIGH
3. All the time
4. When any input is LOW

30. The output of a NOT gate is HIGH when ________.

1. Input changes from LOW to HIGH
2. Voltage is removed from the gate
3. Input is LOW
4. Input is HIGH

31. The output of an OR gate is LOW when ________.

1. All inputs are HIGH
2. All inputs are LOW
3. Any input is LOW
4. Any input is HIGH

32. The Ex-NOR is sometimes called the ________.

1. Inverted OR
2. Parity gate or the equality gate
3. Parity gate
4. Equality gate

33. A logic circuit that provides a HIGH output if one input or the other input, but not both, is HIGH, is a(n):

1. Ex-OR gate
2. NAND gate
3. Ex-NOR gate
4. OR gate

34. The output of an AND gate with three inputs, A, B, and C, is HIGH when ________.

1. A = 1, B = 1, C = 1
2. A = 1, B = 0, C = 1
3. A = 1, B = 1, C = 0
4. A = 0, B = 0, C = 0

35. When used with an IC, what does the term "QUAD" indicate?

1. 6 circuits
2. 8 circuits1
3. 2 circuits
4. 4 circuits

36. The output of an OR gate with three inputs, A, B, and C, is LOW when ________.

1. LA = 0, B = 1, C = 1
2. All of the above
3. A = 0, B = 0, C = 0
4. A = 0, B = 0, C = 1

37. Which of the following logical operations is represented by the + sign in Boolean algebra?

1. OR
2. Complementation
3. Inversion
4. AND

38. Output will be a LOW for any case when one or more inputs are zero for a(n):

1. AND gate
2. NOR gate
3. OR gate
4. NOT gate

39. A basic multiplexer principle can be demonstrated through the use of a:

1. Rotary switch
2. Linear stepper
3. Single-pole relay
4. DPDT switch

40. One multiplexer can take the place of:

1. Several Ex-NOR gates
2. Several SSI logic gates or combinational logic circuits
3. Several SSI logic gates
4. Combinational logic circuits

41. The inputs/outputs of an analog multiplexer/demultiplexer are:

1. Even parity
2. Binary-coded decimal
3. Bidirectional
4. Unidirectional

42. One application of a digital multiplexer is to facilitate:

1. Parity checking
2. Data selector
3. Data generation
4. Serial-to-parallel conversion

43. How many select lines would be required for an 8-line-to-1-line multiplexer?

1. 4
2. 8
3. 2
4. 3

44. Which of the following is correct for a gated D-type flip-flop?

1. Only one of the inputs can be HIGH at a time
2. The output toggles if one of the inputs is held HIGH
3. The Q output is either SET or RESET as soon as the D input goes HIGH or LOW
4. The output complement follows the input when enabled

45. Which of the following describes the operation of a positive edge-triggered D-type flip-flop?

1. When both inputs are LOW, an invalid state exists
2. The input is toggled into the flip-flop on the leading edge of the clock and is passed to the output on the trailing edge of the clock
3. If both inputs are HIGH, the output will toggle
4. The output will follow the input on the leading edge of the clock

46. Which of the following is correct for a D latch?

1. Only one of the inputs can be HIGH at a time
2. The output complement follows the input when enabled
3. The output toggles if one of the inputs is held HIGH
4. Q output follows the input D when the enable is HIGH

47. A D flip-flop utilizing a PGT clock is in the CLEAR state. Which of the following input actions will cause it to change states?

1. CLOCK NGT, D = 1
2. CLOCK PGT, D = 1
3. CLK = NGT, D = 0
4. CLK = PGT, D = 0

48. A positive edge-triggered D flip-flop will store a 1 when ________

1. the D input is HIGH and the clock is LOW
2. the D input is HIGH and the clock is HIGH
3. the D input is HIGH and the clock transitions from HIGH to LOW
4. the D input is HIGH and the clock transitions from LOW to HIGH

49. If an input is activated by a signal transition, it is ________

1. clock triggered
2. noise triggered
3. edge-triggered
4. toggle triggered

50. A basic S-R flip-flop can be constructed by cross-coupling which basic logic gates?

1. NOR or NAND gates
2. AND or NOR gates
3. AND or OR gates
4. XOR or XNOR gates