51. One example of the use of an S-R flip-flop is as a(n)
52. If both inputs of an S-R NAND latch are LOW, what will happen to the output?
53. The truth table for an S-R flip-flop has how many VALID entries?
54. What is one disadvantage of an S-R flip-flop?
55. How can the cross-coupled NAND flip-flop be made to have active-HIGH S-R inputs?
56. On a positive edge-triggered S-R flip-flop, the outputs reflect the input condition when ________
57. What is the hold condition of a flip-flop?
58. If an active-HIGH S-R latch has a 0 on the S input and a 1 on the R input and then the R input goes to 0, the latch will be ________?
59. What is one disadvantage of an S-R flip-flop?
60. The terminal count of a 3-bit binary counter in the DOWN mode is ________?
MCQ Multiple Choice Questions and Answers on Digital Electronics
Digital Electronics Question and Answer